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/external/libxaac/decoder/armv7/
Dixheaacd_esbr_qmfsyn64_winadd.s56 VLD1.32 {D6, D7}, [R2], R9
59 VMLAL.S32 Q14, D7, D5
94 VLD1.32 {D6, D7}, [R12], R9
97 VMLAL.S32 Q14, D7, D5
149 VLD1.32 {D6, D7}, [R2], R9
152 VMLAL.S32 Q14, D7, D5
187 VLD1.32 {D6, D7}, [R12], R9
190 VMLAL.S32 Q14, D7, D5
238 VLD1.32 {D6, D7}, [R2], R9
241 VMLAL.S32 Q14, D7, D5
[all …]
Dixheaacd_calc_post_twid.s41 VLD1.32 {D6, D7}, [R2]!
48 VMULL.S32 Q9, D7, D3
49 VMULL.S32 Q10, D7, D1
56 VSHRN.S64 D7, Q8, #32
63 VSUB.I32 D2, D7, D9
Dixheaacd_overlap_add1.s47 VLD1.32 {D6, D7}, [R10], R12
55 VUZP.16 D7, D6
70 VMULL.U16 Q15, D7, D2
96 VLD1.32 {D6, D7}, [R10], R12
111 VUZP.16 D7, D6
125 VMULL.U16 Q15, D7, D2
140 VLD1.32 {D6, D7}, [R10], R12
166 VUZP.16 D7, D6
172 VMULL.U16 Q15, D7, D2
210 VLD1.32 {D6, D7}, [R10], R12
[all …]
Dixheaacd_pre_twiddle_compute.s114 VLD4.16 {D4, D5, D6, D7}, [R1], R8
156 VMLAL.S16 Q10, D7, D11
162 VMLAL.S16 Q8, D7, D10
176 VLD4.16 {D4, D5, D6, D7}, [R1], R8
229 VMLAL.S16 Q10, D7, D11
231 VMLAL.S16 Q8, D7, D10
240 VLD4.16 {D4, D5, D6, D7}, [R1], R8
287 VMLAL.S16 Q10, D7, D11
289 VMLAL.S16 Q8, D7, D10
321 VLD2.32 {D5, D7}, [R1]!
[all …]
Dixheaacd_post_twiddle.s103 VLD4.16 {D4, D5, D6, D7}, [R1]!
151 VMLAL.S16 Q11, D7, D9
153 VMLAL.S16 Q9, D7, D8
207 VLD4.16 {D4, D5, D6, D7}, [R1]!
259 VMLAL.S16 Q11, D7, D9
261 VMLAL.S16 Q9, D7, D8
313 VLD4.16 {D4, D5, D6, D7}, [R1]!
367 VMLAL.S16 Q11, D7, D9
369 VMLAL.S16 Q9, D7, D8
425 VMOV.S32 D7, #0x00000000
[all …]
Dixheaacd_calcmaxspectralline.s32 VMOV.S32 D7, #0x00000000
53 VMOV.32 R2, D7[0]
55 VMOV.32 R3, D7[1]
Dixheaacd_calc_pre_twid.s40 VLD2.32 {D6, D7}, [R0]!
47 VNEG.S32 D7, D6
53 VMULL.S32 Q10, D1, D7
Dixheaacd_sbr_qmfsyn64_winadd.s77 VLD1.16 D7, [R2], R9
80 VMLAL.S16 Q13, D7, D6
149 VLD1.16 D7, [R2], R9
193 VMLAL.S16 Q13, D7, D6
225 VLD1.16 D7, [R2], R9
236 VMLAL.S16 Q13, D7, D6
301 VLD1.16 D7, [R2], R9
350 VMLAL.S16 Q13, D7, D6
Dixheaacd_overlap_add2.s54 VLD2.16 {D6, D7}, [R7], R12
57 VREV64.16 D5, D7
83 VLD2.16 {D6, D7}, [R7], R12
87 VREV64.16 D5, D7
156 VLD1.32 {D6, D7}, [R10], R12
161 VREV64.32 D1, D7
207 VLD1.32 {D6, D7}, [R10], R12
Dixheaacd_mps_synt_post_fft_twiddle.s41 VLD1.32 {D6, D7}, [R4]!
46 VMULL.S32 Q7, D3, D7
Dixheaacd_sbr_qmfanal32_winadds.s106 VLD2.16 {D7, D8}, [R2]!
111 VMLAL.S16 Q15, D6, D7
200 VLD2.16 {D7, D8}, [R2]!
205 VMLAL.S16 Q15, D6, D7
Dixheaacd_mps_synt_out_calc.s27 VLD2.32 {D6, D7}, [R3]!
33 VMULL.S32 Q7, D3, D7
Dixheaacd_post_twiddle_overlap.s205 VUZP.16 D6, D7
273 VMLAL.S16 Q13, D7, D8
274 VMLAL.S16 Q0, D7, D9
417 VUZP.16 D6, D7
428 VUZP.16 D6, D7
529 VMLAL.S16 Q13, D7, D8
530 VMLAL.S16 Q0, D7, D9
680 VUZP.16 D6, D7
691 VUZP.16 D6, D7
803 VMLAL.S16 Q13, D7, D8
[all …]
/external/iptables/extensions/
Dlibipt_CLUSTERIP.t2 -d 10.31.3.236/32 -i lo -j CLUSTERIP --new --hashmode sourceip --clustermac 01:AA:7B:47:F7:D7 --tot…
3 -d 10.31.3.236/32 -i lo -j CLUSTERIP --new --hashmode sourceip --clustermac 01:AA:7B:47:F7:D7 --tot…
4 -d 10.31.3.236/32 -i lo -j CLUSTERIP --new --hashmode sourceip --clustermac 01:AA:7B:47:F7:D7 --tot…
/external/clang/test/CXX/special/class.inhctor/
Dp7.cpp43 struct D7 : B5 { struct
45 template<typename T> D7(T, ...);
48 D7 d7(0);
/external/llvm-project/clang/test/CXX/special/class.inhctor/
Dp7.cpp43 struct D7 : B5 { struct
45 template<typename T> D7(T, ...);
48 D7 d7(0);
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s173 VLD1.U8 {D6,D7},[R1],R5 @LOAD 17-32 pred row 1
180 VSUBL.U8 Q11,D3,D7 @ Get residue 25-32 row 1 -- dual issue
192 VABAL.U8 Q15,D3,D7
215 VSWP D6,D7 @ Q3: 32 31 30 29 28 27 26 25 row 2
343 VMLAL.S16 Q4,D7,D1 @eo[0][4-7]* R2
354 VMLAL.S16 Q13,D7,D1 @eo[1][4-7]* R2
369 VMLAL.S16 Q12,D7,D1 @eo[2][4-7]* R2
384 VMLAL.S16 Q15,D7,D1 @eo[3][4-7]* R2
409 VMLAL.S16 Q4,D7,D5 @eo[0][4-7]* R2
424 VMLAL.S16 Q8,D7,D5 @eo[0][4-7]* R2
[all …]
Dihevc_sao_edge_offset_class1_chroma.s125 VLD1.8 D7,[r6] @offset_tbl_u = vld1_s8(pi1_sao_offset_u)
189 VTBL.8 D12,{D7},D12 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
205 @VTBL.8 D13,D7,D13 @offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
209 VTBL.8 D24,{D7},D22 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
214 @VTBL.8 D24,D7,D22 @II offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
216 … @VTBL.8 D25,D7,D23 @II offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
259 VTBL.8 D24,{D7},D22
263 @VTBL.8 D24,D7,D22 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
269 @VTBL.8 D25,D7,D23 @offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
340 VTBL.8 D12,{D7},D12
[all …]
/external/llvm-project/clang/test/CXX/special/class.copy/
Dp23-cxx11.cpp122 struct D7 { struct
137 template struct CopyAssign<D7>; // expected-note {{here}} argument
138 template struct MoveAssign<D7>; // expected-note {{here}}
139 template struct MoveOrCopyAssign<D7>; // expected-note {{here}}
/external/clang/test/CXX/special/class.copy/
Dp23-cxx11.cpp122 struct D7 { struct
137 template struct CopyAssign<D7>; // expected-note {{here}} argument
138 template struct MoveAssign<D7>; // expected-note {{here}}
139 template struct MoveOrCopyAssign<D7>; // expected-note {{here}}
/external/toybox/tests/files/bc/
Dprint_results.txt3702 D7
3705 D7.290
4097 .D7
4098 1.D7
4099 60.D7
4544 D7
4547 D7.306
4979 .D7
4980 1.D7
4981 54.D7
[all …]
/external/llvm/unittests/Support/
DAlignOfTest.cpp59 struct D7 : S1, S3 {}; struct
141 [AlignOf<D7>::Alignment > 0]
182 EXPECT_LE(alignOf<S1>(), alignOf<D7>()); in TEST()
264 EXPECT_EQ(alignOf<D7>(), alignOf<AlignedCharArrayUnion<D7> >()); in TEST()
319 EXPECT_EQ(sizeof(D7), sizeof(AlignedCharArrayUnion<D7>)); in TEST()
/external/python/cryptography/vectors/cryptography_vectors/ciphers/Camellia/
Dcamellia-128-ecb.txt18 C No.004 : 5D BE 1E AC 9F 70 80 A8 8D BE D7 F6 DA 10 14 48
66 C No.020 : F1 CD F0 F8 D7 B3 FF D9 54 22 D7 CC 0C F4 0B 7B
246 C No.080 : 42 D7 D6 B1 F4 99 D4 12 F8 79 39 72 BD 96 8D A2
252 C No.082 : 57 6C 26 DF D7 04 6F 93 57 F3 4B EA 7D FB 26 A0
273 C No.089 : F8 E5 C7 FF 4B 79 D7 AB E8 BF A2 DD 14 88 20 A8
351 C No.115 : 16 45 FF AA 8A D7 66 89 C0 1D A8 C4 08 82 78 1F
357 C No.117 : 84 1F D8 AF 69 CF 2C 31 F7 D4 D7 B6 95 96 62 B5
437 C No.015 : 9E D7 49 52 90 3C 1E 70 E3 63 23 44 79 69 62 9A
440 C No.016 : C1 92 DD 83 19 DB 22 0E 8C 35 D7 3B 4D F7 5F 18
452 C No.020 : AE C0 46 16 D7 02 DD 70 51 DD C5 EB 17 95 18 45
[all …]
Dcamellia-192-ecb.txt18 C No.004 : 38 96 55 92 D7 28 F9 B7 65 14 0C 0A 36 A1 BC CD
123 C No.039 : D1 76 3F C0 19 D7 7C C9 30 BF F2 A5 6F 7C 93 64
141 C No.045 : 41 69 45 C1 D1 90 22 38 C4 29 55 CF F1 66 D7 05
165 C No.053 : 92 F2 80 56 13 A8 2E E2 55 68 B3 2E D7 55 0D CC
255 C No.083 : D7 E9 51 24 85 B9 E5 E4 09 FB 51 E2 6D 26 97 95
273 C No.089 : E3 00 D7 41 7C 4F 54 7D BC D5 FC 84 E3 83 3A 7B
330 C No.108 : 4F 5D 37 D7 D0 DC 77 14 E6 2B E4 A0 33 1D B0 7B
369 C No.121 : D7 62 9F 1D D3 95 A9 85 AF 94 97 F6 AC B4 ED A1
398 C No.002 : 2E 0E CB FC 86 39 94 D7 53 C5 12 C9 B4 C4 42 92
431 C No.013 : B3 E0 D7 0C 2C 60 26 EF 32 AD 74 8A 78 F2 2C 91
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfp16-v16-instructions.ll31 ; CHECK-DAG: scvtf [[D7:v[0-9]+\.2d]], v7.2d
41 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
82 ; CHECK-DAG: ucvtf [[D7:v[0-9]+\.2d]], v7.2d
92 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]

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