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Searched refs:DCLZ (Results 1 – 18 of 18) sorted by relevance

/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_64.c225 …FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | TA(EQUAL_FLAG) | DA(EQUAL_FLAG), EQUA… in emit_single_op()
227 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | T(dst) | D(dst), DR(dst))); in emit_single_op()
DsljitNativeMIPS_common.c258 #define DCLZ (LO(18)) macro
260 #define DCLZ (HI(28) | LO(36)) macro
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td296 def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td352 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
DMipsScheduleGeneric.td125 DCLZ, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU,
/external/llvm-project/llvm/lib/Target/Mips/
DMips64InstrInfo.td352 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
DMipsScheduleGeneric.td125 DCLZ, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1073 {DBGFIELD("DCLZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #813
2757 {DBGFIELD("DCLZ") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #813
DMipsGenMCCodeEmitter.inc1299 UINT64_C(1879048228), // DCLZ
4747 case Mips::DCLZ: {
10761 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1286
DMipsGenAsmWriter.inc2527 26245U, // DCLZ
5281 0U, // DCLZ
DMipsGenFastISel.inc192 return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
DMipsGenInstrInfo.inc1301 DCLZ = 1286,
3593 DCLZ = 813,
6147 …86, 2, 1, 4, 813, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1286 = DCLZ
DMipsGenDisassemblerTables.inc7050 /* 984 */ MCD::OPC_Decode, 134, 10, 247, 2, // Opcode: DCLZ
DMipsGenAsmMatcher.inc6302 …{ 3170 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_…
DMipsGenGlobalISel.inc23935 … // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
23936 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ,
DMipsGenDAGISel.inc12224 /* 22790*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLZ), 0,
12227 // Dst: (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc571 25533U, // DCLZ
2360 0U, // DCLZ
DMipsGenDisassemblerTables.inc4680 /* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ