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Searched refs:DDR_GRF_BASE (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c498 sram_data.ddr_grf_con0 = mmio_read_32(DDR_GRF_BASE + in ddr_suspend()
500 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()
510 while ((mmio_read_32(DDR_GRF_BASE + DDRGRF_SOC_STATUS(1)) & in ddr_suspend()
547 while ((mmio_read_32(DDR_GRF_BASE + DDRGRF_SOC_STATUS(1)) & in dmc_restore()
551 mmio_write_32(DDR_GRF_BASE, sram_data.ddr_grf_con0 | 0xc0000000); in dmc_restore()
/external/arm-trusted-firmware/plat/rockchip/rk3328/
Drk3328_def.h88 #define DDR_GRF_BASE 0xff798000 macro
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/
Dsoc.c56 MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE,