| /external/tensorflow/tensorflow/lite/micro/tools/make/targets/ |
| D | arc_emsdp_makefile.inc | 38 BIN_DIR = .$(DLR)\(PS\)bin\n\
39 BIN_FILE = $(DLR)\(BIN_DIR\)$(DLR)\(PS\)app.elf\n
42 $(DLR)\(BIN_FILE\): $(DLR)\(BIN_DIR\) $(DLR)\(OUT_NAME\)\
43 \n\t\@$(DLR)\(CP\) $(DLR)\(OUT_NAME\) $(DLR)\(BIN_FILE\)\
45 \n$(DLR)\(BIN_DIR\):\
46 \n\t\@$(DLR)\(MKDIR\) $(DLR)\(BIN_DIR\)\
48 ARC_EXTRA_RM_TARGETS = $(DLR)\(BIN_DIR\)
50 ARC_BIN_DEPEND = $(DLR)\(BIN_DIR\) $(DLR)\(BIN_FILE\)
51 …ARC_BIN_RULE = \t@echo Copy content of $(DLR)\(BIN_DIR\) into the root of SD card and follow instr…
53 ARC_APP_RUN_CMD = mdb -run -digilent -nooptions $(DLR)\(DBG_ARGS\)
[all …]
|
| /external/tensorflow/tensorflow/lite/micro/tools/make/targets/arc/ |
| D | arc_common.inc | 20 DLR := $$$$
42 ARC_BIN_RULE ?= \t$(DLR)\(error Flash rule isnt defined for this ARC target\)
84 ARC_APP_RUN_CMD = mdb -run -jit -tcf=$(TCF_FILE_NAME) $(DLR)\(DBG_ARGS\)
85 ARC_APP_DEBUG_CMD = mdb -OK -jit -tcf=$(TCF_FILE_NAME) $(DLR)\(DBG_ARGS\)
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | RAbasic-invalid-LR-update.mir | 212 %58 = DLR %58, %53
218 %67 = DLR %67, %62
224 %80 = DLR %80, %75
230 %90 = DLR %90, %85
|
| D | int-div-02.ll | 170 ; Check that divisions of spilled values can use DL rather than DLR.
|
| /external/tensorflow/tensorflow/lite/micro/tools/make/ext_libs/ |
| D | arc_mli.inc | 96 \nifeq \($(DLR)\(MLI_ONLY\), true\)\
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-div-02.ll | 170 ; Check that divisions of spilled values can use DL rather than DLR.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1389 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;
1409 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
|
| D | SystemZScheduleZ13.td | 490 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| D | SystemZScheduleZ15.td | 513 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| D | SystemZScheduleZ14.td | 499 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1402 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;
1422 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
|
| D | SystemZScheduleZ13.td | 490 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| D | SystemZScheduleZ14.td | 499 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| D | SystemZScheduleZ15.td | 513 def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1195 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 3328 16806025U, // DLR
6131 0U, // DLR
8934 0U, // DLR
|
| D | SystemZGenDisassemblerTables.inc | 1730 /* 6912 */ MCD_OPC_Decode, 204, 8, 10, // Opcode: DLR
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l476xx.h | 686 …__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset… member
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart2.csv | 1557 ,"GB","DLR","Dollar","Dollar","CLK","--3-----","RL","0901",,"5609N 00340W",
20835 ,"NL","DLR","De Lier","De Lier",,"--3-----","AF","9602",,,
|
| D | 2013-1_UNLOCODE_CodeListPart1.csv | 15376 ,"CZ","DLR","Doln� Rychnov","Dolni Rychnov","KA","-----6--","RQ","0907",,"5009N 01238E",
35172 ,"FR","DLR","D�ville-l�s-Rouen","Deville-les-Rouen","76","--3-----","RL","0601",,"4927N 00102E",
|
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 13456 ,"US","DLR","Dal-nor","Dal-nor","TX","-23-----","RL","0207",,,"Near Dallas"
|