| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 149 def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
575 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
654 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 176 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
822 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
1020 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
1029 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 176 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
822 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
1020 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
1029 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 499 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 191 #define DSLLV (HI(0) | LO(20)) macro
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3552 SecondShift = Mips::DSLLV; in expandDRotation()
3555 FirstShift = Mips::DSLLV; in expandDRotation()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1083 {DBGFIELD("DSLLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #823
2767 {DBGFIELD("DSLLV") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #823
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| D | MipsGenMCCodeEmitter.inc | 1410 UINT64_C(20), // DSLLV
5268 case Mips::DSLLV:
10872 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1397
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| D | MipsGenAsmWriter.inc | 2638 268459889U, // DSLLV
5392 0U, // DSLLV
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| D | MipsGenAsmMatcher.inc | 6488 …{ 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_Has…
6490 …{ 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_Has…
6494 …{ 3878 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_Ha…
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| D | MipsGenGlobalISel.inc | 13274 …} GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:…
13281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
13293 …// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } …
13294 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
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| D | MipsGenInstrInfo.inc | 1412 DSLLV = 1397,
3603 DSLLV = 823,
6258 …7, 3, 1, 4, 823, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1397 = DSLLV
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| D | MipsGenDAGISel.inc | 19645 /* 36700*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
19648 …// Dst: (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$r…
19674 /* 36754*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
19677 // Dst: (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
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| D | MipsGenDisassemblerTables.inc | 6879 /* 99 */ MCD::OPC_Decode, 245, 10, 238, 2, // Opcode: DSLLV
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 656 134241475U, // DSLLV
2445 0U, // DSLLV
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| D | MipsGenDisassemblerTables.inc | 4284 /* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5020 SecondShift = Mips::DSLLV; in expandDRotation()
5023 FirstShift = Mips::DSLLV; in expandDRotation()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4910 SecondShift = Mips::DSLLV; in expandDRotation()
4913 FirstShift = Mips::DSLLV; in expandDRotation()
|