/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIFixupVectorISel.cpp | 96 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg()); in findSRegBaseAndIndex() local 97 switch (DefInst->getOpcode()) { in findSRegBaseAndIndex() 101 Worklist.push_back(&DefInst->getOperand(1)); in findSRegBaseAndIndex() 104 if (DefInst->getNumOperands() != 5) in findSRegBaseAndIndex() 106 Worklist.push_back(&DefInst->getOperand(1)); in findSRegBaseAndIndex() 107 Worklist.push_back(&DefInst->getOperand(3)); in findSRegBaseAndIndex() 113 if (DefInst->getOperand(2).getSubReg() != AMDGPU::NoSubRegister) in findSRegBaseAndIndex() 115 BaseReg = DefInst->getOperand(2).getReg(); in findSRegBaseAndIndex() 116 if (DefInst->getOperand(3).getSubReg() != AMDGPU::NoSubRegister) in findSRegBaseAndIndex() 118 IndexReg = DefInst->getOperand(3).getReg(); in findSRegBaseAndIndex()
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/external/llvm-project/llvm/lib/Target/BPF/ |
D | BPFMISimplifyPatchable.cpp | 108 MachineInstr *DefInst = I->getParent(); in checkADDrr() local 109 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() 123 const MachineOperand &ImmOp = DefInst->getOperand(2); in checkADDrr() 133 const MachineOperand &Opnd = DefInst->getOperand(0); in checkADDrr() 138 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) in checkADDrr() 139 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr() 141 DefInst->eraseFromParent(); in checkADDrr() 273 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD() local 274 if (!DefInst) in removeLD() 277 if (DefInst->getOpcode() != BPF::LD_imm64) in removeLD() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
D | BPFMISimplifyPatchable.cpp | 105 MachineInstr *DefInst = I->getParent(); in checkADDrr() local 106 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() 120 const MachineOperand &ImmOp = DefInst->getOperand(2); in checkADDrr() 124 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) in checkADDrr() 125 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr() 127 DefInst->eraseFromParent(); in checkADDrr() 257 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD() local 258 if (!DefInst) in removeLD() 263 if (DefInst->getOpcode() == BPF::LD_imm64) { in removeLD() 264 const MachineOperand &MO = DefInst->getOperand(1); in removeLD()
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/external/llvm/lib/Target/AMDGPU/ |
D | SILowerI1Copies.cpp | 110 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction() local 111 if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) { in runOnMachineFunction() 112 if (DefInst->getOperand(1).isImm()) { in runOnMachineFunction() 115 int64_t Val = DefInst->getOperand(1).getImm(); in runOnMachineFunction()
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/external/deqp-deps/SPIRV-Tools/source/fuzz/ |
D | fuzzer_pass_adjust_function_controls.cpp | 39 function.DefInst().GetSingleWordInOperand(0); in Apply() 64 function.DefInst().result_id(), new_function_control_mask); in Apply()
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D | transformation_set_function_control.cpp | 91 if (function.DefInst().result_id() == message_.function_id()) { in FindFunctionDefInstruction() 92 return &function.DefInst(); in FindFunctionDefInstruction()
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D | fuzzer_pass_add_parameters.cpp | 138 function.DefInst().GetSingleWordInOperand(1)); in GetNumberOfParameters()
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D | transformation_permute_function_parameters.cpp | 47 if (!function || function->DefInst().opcode() != SpvOpFunction || in IsApplicable()
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/external/swiftshader/third_party/SPIRV-Tools/source/fuzz/ |
D | fuzzer_pass_adjust_function_controls.cpp | 39 function.DefInst().GetSingleWordInOperand(0); in Apply() 64 function.DefInst().result_id(), new_function_control_mask); in Apply()
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D | transformation_set_function_control.cpp | 91 if (function.DefInst().result_id() == message_.function_id()) { in FindFunctionDefInstruction() 92 return &function.DefInst(); in FindFunctionDefInstruction()
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D | fuzzer_pass_add_parameters.cpp | 138 function.DefInst().GetSingleWordInOperand(1)); in GetNumberOfParameters()
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D | transformation_permute_function_parameters.cpp | 47 if (!function || function->DefInst().opcode() != SpvOpFunction || in IsApplicable()
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D | transformation_wrap_early_terminator_in_function.cpp | 172 if (function.DefInst().GetSingleWordInOperand(1) != void_function_type_id) { in MaybeGetWrapperFunction()
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/external/llvm/lib/Transforms/Scalar/ |
D | EarlyCSE.cpp | 282 Instruction *DefInst; member 288 : DefInst(nullptr), Generation(0), MatchingId(-1), IsAtomic(false), in LoadValue() 292 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue() 637 if (InVal.DefInst != nullptr && in processNode() 644 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); in processNode() 647 << " to: " << *InVal.DefInst << '\n'); in processNode() 715 if (InVal.DefInst && in processNode() 716 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) && in processNode()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
D | EarlyCSE.cpp | 520 Instruction *DefInst = nullptr; member 528 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue() 1115 if (InVal.DefInst != nullptr && in processNode() 1123 InVal.DefInst, Inst))) { in processNode() 1124 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); in processNode() 1127 << " to: " << *InVal.DefInst << '\n'); in processNode() 1208 if (InVal.DefInst && in processNode() 1209 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) && in processNode() 1215 InVal.DefInst, Inst))) { in processNode()
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/external/llvm-project/llvm/lib/Transforms/Scalar/ |
D | EarlyCSE.cpp | 538 Instruction *DefInst = nullptr; member 546 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue() 1081 if (InVal.DefInst == nullptr) in getMatchingValue() 1096 Instruction *Matching = MemInstMatching ? MemInst.get() : InVal.DefInst; in getMatchingValue() 1097 Instruction *Other = MemInstMatching ? InVal.DefInst : MemInst.get(); in getMatchingValue() 1104 if (MemInst.isStore() && InVal.DefInst != Result) in getMatchingValue() 1113 if (!isNonTargetIntrinsicMatch(cast<IntrinsicInst>(InVal.DefInst), in getMatchingValue() 1119 !isSameMemGeneration(InVal.Generation, CurrentGeneration, InVal.DefInst, in getMatchingValue() 1377 << " to: " << *InVal.DefInst << '\n'); in processNode() 1458 if (InVal.DefInst && in processNode() [all …]
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCPreEmitPeephole.cpp | 253 MachineBasicBlock::iterator DefInst; in addLinkerOpt() member 315 MachineBasicBlock::iterator BBI = Pair->DefInst; in addLinkerOpt() 338 Pair->DefInst->addOperand(ImplDef); in addLinkerOpt() 347 Pair->DefInst->addOperand(*MF, PCRelLabel); in addLinkerOpt()
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D | PPCBranchCoalescing.cpp | 467 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd() local 468 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { in canMoveToEnd()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 400 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local 401 if (!DefInst) in findPotentialNewifiableTFRs() 403 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs() 408 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs() 419 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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/external/deqp-deps/SPIRV-Tools/source/opt/ |
D | function.h | 54 Instruction& DefInst() { return *def_inst_; } in DefInst() function 55 const Instruction& DefInst() const { return *def_inst_; } in DefInst() function
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/external/swiftshader/third_party/SPIRV-Tools/source/opt/ |
D | function.h | 54 Instruction& DefInst() { return *def_inst_; } in DefInst() function 55 const Instruction& DefInst() const { return *def_inst_; } in DefInst() function
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCBranchCoalescing.cpp | 462 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd() local 463 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { in canMoveToEnd()
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 416 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local 417 if (!DefInst) in findPotentialNewifiableTFRs() 419 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs() 424 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs() 435 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 414 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local 415 if (!DefInst) in findPotentialNewifiableTFRs() 417 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs() 422 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs() 433 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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/external/swiftshader/third_party/subzero/src/ |
D | IceRegAlloc.cpp | 519 const Inst *DefInst = VMetadata->getFirstDefinitionSingleBlock(Iter.Cur); in findRegisterPreference() local 520 if (DefInst == nullptr) in findRegisterPreference() 523 assert(DefInst->getDest() == Iter.Cur); in findRegisterPreference() 525 DefInst->isVarAssign() && !VMetadata->isMultiDef(Iter.Cur); in findRegisterPreference() 526 FOREACH_VAR_IN_INST(SrcVar, *DefInst) { in findRegisterPreference()
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