| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitConst32AndConst64.cpp | 89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction() local
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo) in runOnMachineFunction()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IcePhiLoweringImpl.h | 41 auto *DestLo = llvm::cast<Variable>(Target->loOperand(Dest)); in prelowerPhis32Bit() local
43 auto *PhiLo = InstPhi::create(Func, Phi->getSrcSize(), DestLo); in prelowerPhis32Bit()
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| D | IceTargetLoweringARM32.cpp | 2589 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerInt64Arithmetic() local
2591 Variable *T_Lo = makeReg(DestLo->getType()); in lowerInt64Arithmetic()
2604 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2615 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2626 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2637 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2649 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2654 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2691 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2701 _mov(DestLo, Src0RLo); in lowerInt64Arithmetic()
[all …]
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| D | IceTargetLoweringX86BaseImpl.h | 1766 Operand *Src1Lo, Variable *DestLo,
1789 _mov(DestLo, Zero);
1799 _mov(DestLo, T_2);
1814 _mov(DestLo, T_2);
1830 _mov(DestLo, Zero);
1838 _mov(DestLo, T_2);
1849 _mov(DestLo, T_2);
1890 _mov(DestLo, T_2);
1971 _mov(DestLo, T_2);
2023 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
[all …]
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| D | IceTargetLoweringMIPS32.cpp | 2038 Variable *DestLo = Target->makeReg( in legalizeMov() local
2051 Target->_mov(DestLo, Reg); in legalizeMov()
2454 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); in lowerInt64Arithmetic() local
2473 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2487 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2500 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2514 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2526 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
2545 _mov(DestLo, T1); in lowerInt64Arithmetic()
2586 _mov(DestLo, T_Lo); in lowerInt64Arithmetic()
[all …]
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| D | IceTargetLoweringARM32.h | 828 void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
836 Context.insert<InstARM32Umull>(DestLo, DestHi, Src0, Src1, Pred);
837 Context.insert<InstFakeDef>(DestHi, DestLo)->setDestRedefined();
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| D | IceInstARM32.h | 1438 static InstARM32Umull *create(Cfg *Func, Variable *DestLo, Variable *DestHi, in create() argument
1442 InstARM32Umull(Func, DestLo, DestHi, Src0, Src1, Predicate); in create()
1450 InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi, Variable *Src0,
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| D | IceInstARM32.cpp | 1517 InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi, in InstARM32Umull() argument
1520 : InstARM32Pred(Func, InstARM32::Umull, 2, DestLo, Predicate), in InstARM32Umull()
1904 Variable *DestLo = getDest(); in emitMultiDestSingleSource() local
1909 assert(DestLo->hasReg()); in emitMultiDestSingleSource()
1915 DestLo->emit(Func); in emitMultiDestSingleSource()
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| D | IceTargetLoweringX86Base.h | 1128 Operand *Src1Lo, Variable *DestLo, Variable *DestHi);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitConst32AndConst64.cpp | 89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction() local
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo) in runOnMachineFunction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitConst32AndConst64.cpp | 140 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction() local
147 DestLo) in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
57 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo) in copyPhysReg()
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
57 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo) in copyPhysReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 678 MachineOperand &DestLo = MI.getOperand(0); in expandCMP_SWAP_128() local
707 LoadCmpBB->addLiveIn(DestLo.getReg()); in expandCMP_SWAP_128()
714 .addReg(DestLo.getReg(), RegState::Define) in expandCMP_SWAP_128()
718 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead())) in expandCMP_SWAP_128()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 259 MachineOperand &DestLo = MI.getOperand(0); in expandCMP_SWAP_128() local
287 .addReg(DestLo.getReg(), RegState::Define) in expandCMP_SWAP_128()
291 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead())) in expandCMP_SWAP_128()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 264 MachineOperand &DestLo = MI.getOperand(0); in expandCMP_SWAP_128() local
292 .addReg(DestLo.getReg(), RegState::Define) in expandCMP_SWAP_128()
296 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead())) in expandCMP_SWAP_128()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 894 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64() local
932 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64() local
1091 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1689 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64() local
1716 .addReg(DestLo, getKillRegState(Dest.isDead())) in ExpandCMP_SWAP_64()
|