/external/llvm/test/MC/Mips/ |
D | user-macro-argument-separation.s | 12 .macro EX2 insn, rd, imm, rs macro 18 EX2 addiu $2, 1 $3 # CHECK: addiu $2, $3, 1 19 EX2 addiu $2, ~1 $3 # CHECK: addiu $2, $3, -2 20 EX2 addiu $2, ~ 1 $3 # CHECK: addiu $2, $3, -2 21 EX2 addiu $2, 1+1 $3 # CHECK: addiu $2, $3, 2 22 EX2 addiu $2, 1+ 1 $3 # CHECK: addiu $2, $3, 2 23 EX2 addiu $2, 1 +1 $3 # CHECK: addiu $2, $3, 2 24 EX2 addiu $2, 1 + 1 $3 # CHECK: addiu $2, $3, 2 25 EX2 addiu $2, 1+~1 $3 # CHECK: addiu $2, $3, -1 26 EX2 addiu $2, 1+~ 1 $3 # CHECK: addiu $2, $3, -1 [all …]
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/external/llvm-project/llvm/test/MC/Mips/ |
D | user-macro-argument-separation.s | 12 .macro EX2 insn, rd, imm, rs macro 18 EX2 addiu $2, 1 $3 # CHECK: addiu $2, $3, 1 19 EX2 addiu $2, ~1 $3 # CHECK: addiu $2, $3, -2 20 EX2 addiu $2, ~ 1 $3 # CHECK: addiu $2, $3, -2 21 EX2 addiu $2, 1+1 $3 # CHECK: addiu $2, $3, 2 22 EX2 addiu $2, 1+ 1 $3 # CHECK: addiu $2, $3, 2 23 EX2 addiu $2, 1 +1 $3 # CHECK: addiu $2, $3, 2 24 EX2 addiu $2, 1 + 1 $3 # CHECK: addiu $2, $3, 2 25 EX2 addiu $2, 1+~1 $3 # CHECK: addiu $2, $3, -1 26 EX2 addiu $2, 1+~ 1 $3 # CHECK: addiu $2, $3, -1 [all …]
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/external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
D | vert-ex2.sh | 12 EX2 TEMP[0], IN[0] 13 EX2 TEMP[1], IN[1].yyyy
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/external/mesa3d/src/gallium/tests/graw/fragment-shader/ |
D | frag-ex2.sh | 8 EX2 TEMP[0], IN[0].xxxx
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/external/tensorflow/tensorflow/compiler/mlir/tfr/tests/ |
D | control_flow.mlir | 53 // CHECK-NEXT: %[[EX2:.*]] = tfr.call @tf__expand_dims(%[[CAST2]], %[[AXIS]]) : (!tfr.tensor, i32) … 54 // CHECK-NEXT: %[[CONCAT2:.*]] = tfr.call @tf__risc_concat(%[[CONCAT1]], %[[EX2]], %[[AXIS]]) : (!t…
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMScheduleM7.td | 27 // EX2: fast load data ALUs FP operation 31 // There are shifters in both EX1 and EX2, and some instructions can be 32 // flexibly allocated between them. EX2 is used as the "zero" point 33 // for scheduling, so simple ALU operations executing in EX2 will have 326 // shifter but have timing as if they used the EX2 shifter as they usually 327 // can choose the EX2 shifter when needed. Will miss a few dual-issue cases,
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D | ARMScheduleR52.td | 60 // ALU - Write occurs in Late EX2 (independent of whether shift was required) 78 // Branches - LR written in Late EX2
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/external/virglrenderer/src/gallium/auxiliary/tgsi/ |
D | tgsi_opcode_tmp.h | 82 OP11(EX2)
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
D | tgsi_opcode_tmp.h | 68 OP11(EX2)
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D | tgsi_info_opcodes.h | 29 OPCODE(1, 1, REPL, EX2)
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/external/mesa3d/src/mesa/program/ |
D | program_lexer.l | 200 EX2{sat} { return_opcode( 1, SCALAR_OP, EX2, 3); }
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/external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
D | nvfx_fragprog.c | 598 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction() 675 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none)); in nvfx_fragprog_parse_instruction() 689 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none)); in nvfx_fragprog_parse_instruction()
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D | nvfx_vertprog.c | 595 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0])); in nvfx_vertprog_parse_instruction() 641 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X))); in nvfx_vertprog_parse_instruction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMScheduleR52.td | 60 // ALU - Write occurs in Late EX2 (independent of whether shift was required) 78 // Branches - LR written in Late EX2
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SchedA55.td | 178 // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
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/external/llvm-project/llvm/unittests/IR/ |
D | PatternMatch.cpp | 950 Value *EX2 = IRB.CreateExtractElement(VI4, (uint64_t)0); in TEST_F() local 990 EXPECT_TRUE(match(EX2, m_ExtractElt(m_Value(), m_ConstantInt()))); in TEST_F()
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
D | r200_vertprog.c | 80 OPN(EX2, 1|SCALAR_FLAG),
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_from_tgsi.cpp | 752 NV50_IR_OPCODE_CASE(EX2, EX2); in translateOpcode()
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/external/mesa3d/src/gallium/frontends/nine/ |
D | nine_shader.c | 3072 _OPI(EXP, EX2, V(0,0), V(3,0), V(0,0), V(3,0), 1, 1, NULL), /* 14 */ 3137 _OPI(EXPP, EX2, V(2,0), V(3,0), V(0,0), V(0,0), 1, 1, NULL),
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/external/mesa3d/src/gallium/drivers/etnaviv/ |
D | etnaviv_compiler_tgsi.c | 1801 INSTR(EX2, trans_instr, .opc = INST_OPCODE_EXP, .src = {2, -1, -1}),
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/external/mesa3d/docs/gallium/ |
D | tgsi.rst | 327 .. opcode:: EX2 - Exponential Base 2
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