| /external/llvm-project/flang/include/flang/Common/ |
| D | Fortran.h | 51 Delim, Direct, Encoding, End, Eor, Err, Exist, File, Fmt, Form, Formatted,
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| /external/llvm-project/flang/lib/Semantics/ |
| D | check-io.cpp | 190 SetSpecifier(IoSpecKind::Eor); in Enter()
719 CheckForRequiredSpecifier(IoSpecKind::Eor, in Leave()
750 CheckForProhibitedSpecifier(IoSpecKind::Eor); // C1213 in Leave()
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 222 __ Eor(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 76 __ Eor(x11, x0, 0x18001); in TEST() local
533 __ Eor(w13, w0, kWMinInt); in TEST() local
902 __ Eor(x2, x0, Operand(x1)); in TEST() local
903 __ Eor(w3, w0, Operand(w1, LSL, 4)); in TEST() local
904 __ Eor(x4, x0, Operand(x1, LSL, 4)); in TEST() local
905 __ Eor(x5, x0, Operand(x1, LSR, 1)); in TEST() local
906 __ Eor(w6, w0, Operand(w1, ASR, 20)); in TEST() local
907 __ Eor(x7, x0, Operand(x1, ASR, 20)); in TEST() local
908 __ Eor(w8, w0, Operand(w1, ROR, 28)); in TEST() local
909 __ Eor(x9, x0, Operand(x1, ROR, 28)); in TEST() local
[all …]
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| D | test-disasm-aarch64.cc | 2812 COMPARE_MACRO(Eor(w4, w5, 0), "mov w4, w5"); in TEST()
2813 COMPARE_MACRO(Eor(x4, x5, 0), "mov x4, x5"); in TEST()
2828 COMPARE_MACRO(Eor(w16, w17, 0xffffffff), "mvn w16, w17"); in TEST()
2829 COMPARE_MACRO(Eor(x16, x17, 0xffffffff), "eor x16, x17, #0xffffffff"); in TEST()
2830 COMPARE_MACRO(Eor(x16, x17, 0xffffffffffffffff), "mvn x16, x17"); in TEST()
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| D | test-disasm-sve-aarch64.cc | 2319 COMPARE_MACRO(Eor(z23.VnB(), p4.Merging(), z23.VnB(), z15.VnB()), in TEST()
2321 COMPARE_MACRO(Eor(z23.VnH(), p4.Merging(), z23.VnH(), z15.VnH()), in TEST()
2323 COMPARE_MACRO(Eor(z23.VnD(), p4.Merging(), z18.VnD(), z15.VnD()), in TEST()
6199 COMPARE_MACRO(Eor(z12, z3, z17), "eor z12.d, z3.d, z17.d"); in TEST()
6204 COMPARE_MACRO(Eor(z12.VnH(), z3.VnH(), z17.VnH()), "eor z12.d, z3.d, z17.d"); in TEST()
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| D | test-assembler-sve-aarch64.cc | 558 __ Eor(z3.VnD(), z8.VnD(), z15.VnD()); in TEST_SVE() local
1154 __ Eor(p2.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB()); in TEST_SVE() local
1433 __ Eor(z5.VnD(), z5.VnD(), 0x0000ffff0000ffff); in TEST_SVE() local
1434 __ Eor(z6.VnS(), z6.VnS(), 0xff0000ff); in TEST_SVE() local
1435 __ Eor(z7.VnH(), z7.VnH(), 0x0ff0); in TEST_SVE() local
1436 __ Eor(z8.VnB(), z8.VnB(), 0x3f); in TEST_SVE() local
5002 fn = &MacroAssembler::Eor; in TEST_SVE()
9974 __ Eor(pg_diff.VnB(), all.Zeroing(), pg_diff.VnB(), pg_ff.VnB()); in GatherLoadScalarPlusVectorHelper() local
10553 __ Eor(z4.VnB(), z4.VnB(), z0.VnB()); in TEST_SVE() local
10556 __ Eor(z5.VnB(), z5.VnB(), z1.VnB()); in TEST_SVE() local
[all …]
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| D | test-assembler-neon-aarch64.cc | 6087 __ Eor(v16.V16B(), v0.V16B(), v0.V16B()); // self test in TEST() local
6088 __ Eor(v17.V16B(), v0.V16B(), v1.V16B()); // all combinations in TEST() local
6089 __ Eor(v24.V8B(), v0.V8B(), v0.V8B()); // self test in TEST() local
6090 __ Eor(v25.V8B(), v0.V8B(), v1.V8B()); // all combinations in TEST() local
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| D | test-disasm-neon-aarch64.cc | 1770 COMPARE_MACRO(Eor(v6.V8B(), v7.V8B(), v8.V8B()), "eor v6.8b, v7.8b, v8.8b"); in TEST()
1771 COMPARE_MACRO(Eor(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3335 COMPARE_T32(Eor(eq, r0, r0, r7), in TEST()
3339 COMPARE_T32(Eor(eq, r0, r0, 0x1), in TEST()
4043 CHECK_T32_16(Eor(DontCare, r7, r7, r6), "eors r7, r6\n"); in TEST()
4045 CHECK_T32_16_IT_BLOCK(Eor(DontCare, eq, r7, r7, r6), in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 124 M(Eor) \
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| D | test-assembler-aarch32.cc | 3268 __ Eor(r0, r0, 0); in TEST() local
3312 __ Eor(r3, r0, 0xffffffff); in TEST() local
6065 CHECK_SIZE_MATCH(Eor(r7, r7, r6), Eor(r7, r6, r7)); in TEST_T32()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 124 M(Eor) \
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 392 Eor, enumerator
1008 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| D | IceInstARM32.cpp | 3491 template class InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 731 void Eor(const Register& rd, const Register& rn, const Operand& operand);
2703 V(eor, Eor) \
3055 V(eor, Eor) \
4066 void Eor(const PRegisterWithLaneSize& pd, in Eor() function
4074 void Eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in Eor() function
4084 void Eor(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Eor() function
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| D | macro-assembler-aarch64.cc | 802 void MacroAssembler::Eor(const Register& rd, in Eor() function in vixl::aarch64::MacroAssembler
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1694 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { in Eor() function
1718 void Eor(Register rd, Register rn, const Operand& operand) { in Eor() function
1719 Eor(al, rd, rn, operand); in Eor()
1721 void Eor(FlagsUpdate flags, in Eor() function
1728 Eor(cond, rd, rn, operand); in Eor()
1740 Eor(cond, rd, rn, operand); in Eor()
1745 void Eor(FlagsUpdate flags, in Eor() function
1749 Eor(flags, al, rd, rn, operand); in Eor()
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