| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 76 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \
77 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \
78 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \
79 V_(RmLow16, 19, 16, ExtractBits) /* Second source register (code 0-15). */ \
80 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \
81 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \
82 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \
83 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \
84 V_(Pt, 3, 0, ExtractBits) /* Load/store register (p0-p7). */ \
85 V_(Pd, 3, 0, ExtractBits) /* SVE destination predicate register. */ \
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| D | instructions-aarch64.cc | 89 unsigned tsz = ExtractBits<0x00c00300>(); in CanTakeSVEMovprfx()
253 unsigned opc = ExtractBits(23, 22); in CanTakeSVEMovprfx()
254 unsigned opc2 = ExtractBits(18, 17); in CanTakeSVEMovprfx()
394 unsigned opc = ExtractBits(23, 22); in CanTakeSVEMovprfx()
395 unsigned opc2 = ExtractBits(18, 17); in CanTakeSVEMovprfx()
605 uint32_t imm_2 = ExtractBits<0x00C00000>(); in GetSVEPermuteIndexAndLaneSizeLog2()
606 uint32_t tsz_5 = ExtractBits<0x001F0000>(); in GetSVEPermuteIndexAndLaneSizeLog2()
649 is_predicated ? ExtractBits<0x00C00300>() : ExtractBits<0x00D80000>(); in GetSVEImmShiftAndLaneSizeLog2()
651 is_predicated ? ExtractBits<0x000000E0>() : ExtractBits<0x00070000>(); in GetSVEImmShiftAndLaneSizeLog2()
665 Instr dtype_h = ExtractBits(dtype_h_lsb + 1, dtype_h_lsb); in GetSVEMsizeFromDtype()
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| D | instructions-aarch64.h | 237 uint32_t ExtractBits(int msb, int lsb) const { in ExtractBits() function
241 return ExtractBits(msb, lsb);
266 uint32_t ExtractBits() const { in ExtractBits() function
300 return this->ExtractBits(msb, lsb); in INSTRUCTION_FIELDS_LIST()
383 Float16 GetSVEImmFP16() const { return Imm8ToFloat16(ExtractBits(12, 5)); } in GetSVEImmFP16()
385 float GetSVEImmFP32() const { return Imm8ToFP32(ExtractBits(12, 5)); } in GetSVEImmFP32()
387 double GetSVEImmFP64() const { return Imm8ToFP64(ExtractBits(12, 5)); } in GetSVEImmFP64()
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| D | disasm-aarch64.cc | 2869 unsigned index = (instr->ExtractBits(15, 11) << 2) | in VisitNEON3Same()
5072 if (instr->ExtractBits(20, 16) != 0) form = form_imm; in VisitSVE32BitGatherLoad_VectorPlusImm()
5111 const char *form = (instr->ExtractBits(20, 16) != 0) in VisitSVE32BitGatherPrefetch_VectorPlusImm()
5182 bool is_zero = instr->ExtractBits(20, 16) == 0; in VisitSVE32BitScatterStore_VectorPlusImm()
5410 if (instr->ExtractBits(20, 16) != 0) { in VisitSVE64BitGatherLoad_VectorPlusImm()
5411 unsigned msz = instr->ExtractBits(24, 23); in VisitSVE64BitGatherLoad_VectorPlusImm()
5535 const char *form = (instr->ExtractBits(20, 16) != 0) in VisitSVE64BitGatherPrefetch_VectorPlusImm()
5663 bool is_zero = instr->ExtractBits(20, 16) == 0; in VisitSVE64BitScatterStore_VectorPlusImm()
5743 unsigned tsize = (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(9, 8); in VisitSVEBitwiseShiftByImm_Predicated()
5971 int tsz = instr->ExtractBits(20, 16); in VisitSVEBroadcastIndexElement()
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| D | simulator-aarch64.cc | 5950 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) { in NEONLoadStoreMultiStructHelper()
6110 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) { in NEONLoadStoreSingleStructHelper()
7366 int shift_amount = instr->ExtractBits(11, 10); in VisitSVEAddressGeneration()
7636 int multiplier = instr->ExtractBits(19, 16) + 1; in VisitSVEIncDecRegisterByElementCount()
7670 int multiplier = instr->ExtractBits(19, 16) + 1; in VisitSVEIncDecVectorByElementCount()
7706 int multiplier = instr->ExtractBits(19, 16) + 1; in VisitSVESaturatingIncDecRegisterByElementCount()
7783 int multiplier = instr->ExtractBits(19, 16) + 1; in VisitSVESaturatingIncDecVectorByElementCount()
7839 int multiplier = instr->ExtractBits(19, 16) + 1; in VisitSVEElementCount()
7973 ftmad(vform, zd, zd, zm, instr->ExtractBits(18, 16)); in VisitSVEFPTrigMulAddCoefficient()
8125 int rot = instr->ExtractBits(14, 13); in VisitSVEFPComplexMulAdd()
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| D | decoder-aarch64.cc | 183 bit_extract_fn = &Instruction::ExtractBits<M>; \ in GetBitExtractFunction()
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| D | simulator-aarch64.h | 909 uint32_t ExtractBits(int msb, int lsb) const { in ExtractBits() function
913 return ExtractBits(msb, lsb);
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| D | logic-aarch64.cc | 7268 int msize_in_bytes_log2 = instr->ExtractBits(24, 23); in SVEGatherLoadScalarPlusVectorHelper()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULowerKernelArguments.cpp | 203 Value *ExtractBits = OffsetDiff == 0 ? in runOnFunction() local
207 Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy); in runOnFunction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULowerKernelArguments.cpp | 235 Value *ExtractBits = OffsetDiff == 0 ? in runOnFunction() local
239 Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy); in runOnFunction()
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| /external/mdnsresponder/mDNSShared/ |
| D | CommonServices.h | 700 #define ExtractBits( X, MASK, SHIFT ) ( ( ( X ) >> ( SHIFT ) ) & ( ( MASK ) >> ( SHIFT ) ) ) macro
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| /external/vixl/src/ |
| D | utils-vixl.h | 635 inline Td ExtractBits(Ts value, int least_significant_bit, Td mask) { in ExtractBits() function
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