| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | float_arithmetic_operations.mir | 123 ; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
124 ; FP32: $f0 = COPY [[FDIV_S]]
130 ; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
131 ; FP64: $f0 = COPY [[FDIV_S]]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoF.td | 142 def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
144 def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
308 def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoF.td | 141 def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
143 def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
314 def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
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| /external/mesa3d/src/mesa/x86/ |
| D | x86_cliptest.S | 167 FDIV_S( SRC3 ) /* GH: don't care about div-by-zero */
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| D | assyntax.h | 710 #define FDIV_S(a) CHOICE(fdivs a, fdivs a, fdivs a) macro
1423 #define FDIV_S(a) fdiv S_(a) macro
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 471 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 463 def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
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| D | MipsInstrFPU.td | 637 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
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| D | MipsScheduleGeneric.td | 848 def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S)>;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 464 def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
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| D | MipsInstrFPU.td | 670 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
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| D | MipsScheduleGeneric.td | 851 def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S)>;
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 739 134241045U, // FDIV_S
2528 0U, // FDIV_S
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| D | MipsGenDisassemblerTables.inc | 1049 /* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 898 {DBGFIELD("FDIV_S") 1, false, false, 21, 2, 7, 1, 0, 0}, // #638
2582 {DBGFIELD("FDIV_S") 1, false, false, 54, 3, 15, 1, 0, 0}, // #638
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| D | MipsGenMCCodeEmitter.inc | 1518 UINT64_C(1174405123), // FDIV_S
3514 case Mips::FDIV_S:
10980 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1505
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| D | MipsGenAsmWriter.inc | 2746 268459324U, // FDIV_S
5500 0U, // FDIV_S
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| D | MipsGenInstrInfo.inc | 1520 FDIV_S = 1505,
3418 FDIV_S = 638,
6366 …, 3, 1, 4, 638, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1505 = FDIV_S
16790 { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },
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| D | MipsGenFastISel.inc | 1517 return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | MipsGenDisassemblerTables.inc | 3369 /* 2667 */ MCD::OPC_Decode, 225, 11, 207, 1, // Opcode: FDIV_S
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| D | MipsGenAsmMatcher.inc | 6350 …{ 3239 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_H…
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| D | MipsGenGlobalISel.inc | 22375 …// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] …
22376 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
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| D | MipsGenDAGISel.inc | 27641 /* 52275*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_S), 0,
27644 // Dst: (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
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