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Searched refs:FHSUB (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h355 X86_INTRINSIC_DATA(avx_hsub_pd_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
356 X86_INTRINSIC_DATA(avx_hsub_ps_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1082 X86_INTRINSIC_DATA(sse3_hsub_pd, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1083 X86_INTRINSIC_DATA(sse3_hsub_ps, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
DX86ISelLowering.h232 FHSUB, enumerator
DX86InstrFragmentsSIMD.td59 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
DX86ISelLowering.cpp9242 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break; in isHopBuildVector()
9428 X86Opcode = X86ISD::FHSUB; in LowerToHorizontalOp()
20369 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break; in lowerAddSubToHorizontalOp()
29654 case X86ISD::FHSUB: return "X86ISD::FHSUB"; in getTargetNodeName()
34542 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB || in combineTargetShuffle()
35131 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB) in foldShuffleOfHorizOp()
35544 case X86ISD::FHSUB: { in SimplifyDemandedVectorEltsForTargetNode()
35729 case X86ISD::FHSUB: { in SimplifyDemandedVectorEltsForTargetNode()
41939 auto HorizOpcode = IsFadd ? X86ISD::FHADD : X86ISD::FHSUB; in combineFaddFsub()
/external/llvm-project/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h355 X86_INTRINSIC_DATA(avx_hsub_pd_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
356 X86_INTRINSIC_DATA(avx_hsub_ps_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1088 X86_INTRINSIC_DATA(sse3_hsub_pd, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1089 X86_INTRINSIC_DATA(sse3_hsub_ps, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
DX86ISelLowering.h256 FHSUB, enumerator
DX86InstrFragmentsSIMD.td59 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
DX86ISelLowering.cpp9515 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break; in isHopBuildVector()
9701 X86Opcode = X86ISD::FHSUB; in LowerToHorizontalOp()
10867 case X86ISD::FHSUB: in IsElementEquivalent()
21488 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break; in lowerAddSubToHorizontalOp()
30799 NODE_NAME_CASE(FHSUB) in getTargetNodeName()
35887 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB); in canonicalizeShuffleMaskWithHorizOp()
37472 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB) in foldShuffleOfHorizOp()
37891 case X86ISD::FHSUB: { in SimplifyDemandedVectorEltsForTargetNode()
38080 case X86ISD::FHSUB: { in SimplifyDemandedVectorEltsForTargetNode()
42606 X86ISD::HSUB == Opcode || X86ISD::FHSUB == Opcode || in combineHorizOpWithShuffle()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.h235 FHSUB, enumerator
DX86IntrinsicsInfo.h255 X86_INTRINSIC_DATA(avx_hsub_pd_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
256 X86_INTRINSIC_DATA(avx_hsub_ps_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1932 X86_INTRINSIC_DATA(sse3_hsub_pd, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
1933 X86_INTRINSIC_DATA(sse3_hsub_ps, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
DX86InstrFragmentsSIMD.td66 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc11324 // FastEmit functions for X86ISD::FHSUB.
15161 case X86ISD::FHSUB: return fastEmit_X86ISD_FHSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);