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Searched refs:FNP (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp314 const Instruction *FNP = BB->getFirstNonPHI(); in set() local
317 if (const auto *LPI = dyn_cast<LandingPadInst>(FNP)) in set()
/external/llvm/lib/Target/Hexagon/
DHexagonEarlyIfConv.cpp262 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern() local
270 bool FOk = (FNP == 1) && (FNS == 1); in matchFlowPattern()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonEarlyIfConv.cpp286 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern() local
295 bool FOk = (FNP == 1 && FNS == 1 && MLI->getLoopFor(FB) == L); in matchFlowPattern()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonEarlyIfConv.cpp286 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern() local
295 bool FOk = (FNP == 1 && FNS == 1 && MLI->getLoopFor(FB) == L); in matchFlowPattern()
/external/vixl/src/aarch64/
Dsimulator-aarch64.h3984 #define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP) \
3985 LogicVRegister FNP(VectorFormat vform, \
3989 LogicVRegister FNP(VectorFormat vform, \
Dlogic-aarch64.cc5340 #define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP) \ argument
5341 LogicVRegister Simulator::FNP(VectorFormat vform, \
5352 LogicVRegister Simulator::FNP(VectorFormat vform, \
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv12332 ,"US","FNP","Champion","Champion","MI","--3-----","RL","1201",,"4630N 08757W",
D2013-1_UNLOCODE_CodeListPart1.csv15402 ,"CZ","FNP","Frantiskov nad Ploucnici","Frantiskov nad Ploucnici","US","-----6--","RL","0901",,"504…