| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2103 auto Fma1 = B.buildFMA(S32, Fma0, ApproxRcp, ApproxRcp, Flags); in legalizeFDIV32() local
2104 auto Mul = B.buildFMul(S32, NumeratorScaled, Fma1, Flags); in legalizeFDIV32()
2106 auto Fma3 = B.buildFMA(S32, Fma2, Fma1, Mul, Flags); in legalizeFDIV32()
2114 .addUse(Fma1.getReg(0)) in legalizeFDIV32()
2157 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64() local
2158 auto Fma2 = B.buildFMA(S64, NegDivScale0, Fma1, One, Flags); in legalizeFDIV64()
2166 auto Fma3 = B.buildFMA(S64, Fma1, Fma2, Fma1, Flags); in legalizeFDIV64()
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| D | SIISelLowering.cpp | 7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32() local
7767 Fma1, Fma1); in LowerFDIV32()
7772 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul, Fma2); in LowerFDIV32()
7802 Fma4, Fma1, Fma3, Scale); in LowerFDIV32()
7827 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64() local
7829 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
7833 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2211 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, ApproxRcp); in LowerFDIV32() local
2213 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1); in LowerFDIV32()
2216 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul); in LowerFDIV32()
2220 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, Fma4, Fma1, Fma3, Scale); in LowerFDIV32()
2245 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64() local
2247 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
2251 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 3211 auto Fma1 = B.buildFMA(S32, Fma0, ApproxRcp, ApproxRcp, Flags); in legalizeFDIV32() local
3212 auto Mul = B.buildFMul(S32, NumeratorScaled, Fma1, Flags); in legalizeFDIV32()
3214 auto Fma3 = B.buildFMA(S32, Fma2, Fma1, Mul, Flags); in legalizeFDIV32()
3222 .addUse(Fma1.getReg(0)) in legalizeFDIV32()
3264 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64() local
3265 auto Fma2 = B.buildFMA(S64, NegDivScale0, Fma1, One, Flags); in legalizeFDIV64()
3273 auto Fma3 = B.buildFMA(S64, Fma1, Fma2, Fma1, Flags); in legalizeFDIV64()
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| D | SIISelLowering.cpp | 8440 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32() local
8444 Fma1, Fma1, Flags); in LowerFDIV32()
8450 Fma2, Fma1, Mul, Fma2, Flags); in LowerFDIV32()
8480 {Fma4, Fma1, Fma3, Scale}, Flags); in LowerFDIV32()
8505 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64() local
8507 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
8511 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
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