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/external/llvm/test/Transforms/InferFunctionAttrs/
Dannotate.ll14 ; CHECK-NVPTX: declare i32 @__nvvm_reflect(i8*) [[G0:#[0-9]+]]
15 ; CHECK-NVPTX: attributes [[G0]] = { nounwind readnone }
40 ; CHECK: declare i32 @access(i8* nocapture readonly, i32) [[G0:#[0-9]+]]
121 ; CHECK: declare void @bcopy(i8* nocapture readonly, i8* nocapture, i64) [[G0]]
124 ; CHECK: declare void @bzero(i8* nocapture, i64) [[G0]]
127 ; CHECK: declare noalias i8* @calloc(i64, i64) [[G0]]
148 ; CHECK: declare i32 @chmod(i8* nocapture readonly, i16 zeroext) [[G0]]
151 ; CHECK: declare i32 @chown(i8* nocapture readonly, i32, i32) [[G0]]
154 ; CHECK: declare void @clearerr(%opaque* nocapture) [[G0]]
157 ; CHECK: declare i32 @closedir(%opaque* nocapture) [[G0]]
[all …]
/external/llvm-project/llvm/test/Transforms/InferFunctionAttrs/
Dannotate.ll9 ; CHECK: declare noalias noundef nonnull i8* @_Znwj(i64) [[G0:#[0-9]+]]
11 ; CHECK: declare noalias noundef nonnull i8* @_Znwm(i64) [[G0]]
14 ; CHECK-NVPTX: declare noundef i32 @__nvvm_reflect(i8* noundef) [[G0:#[0-9]+]]
15 ; CHECK-NVPTX: attributes [[G0]] = { nofree nounwind readnone }
163 ; CHECK: declare i32 @abs(i32) [[G0]]
169 ; CHECK: declare double @acos(double) [[G0]]
172 ; CHECK: declare float @acosf(float) [[G0]]
175 ; CHECK: declare double @acosh(double) [[G0]]
178 ; CHECK: declare float @acoshf(float) [[G0]]
181 ; CHECK: declare x86_fp80 @acoshl(x86_fp80) [[G0]]
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td138 // t<cond> %icc, rs => t<cond> %icc, G0 + rs
140 (TICCrr G0, IntRegs:$rs2, condVal)>,
148 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
150 (TXCCrr G0, IntRegs:$rs2, condVal)>,
158 // t<cond> rs=> t<cond> %icc, G0 + rs2
160 // (TICCrr G0, IntRegs:$rs2, condVal)>,
168 // t<cond> %icc, imm => t<cond> %icc, G0 + imm
170 (TICCri G0, i32imm:$imm, condVal)>,
176 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
178 (TXCCri G0, i32imm:$imm, condVal)>,
[all …]
DDelaySlotFiller.cpp417 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
418 && OrMI->getOperand(2).getReg() != SP::G0) in combineRestoreOR()
422 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
489 && MBBI->getOperand(0).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
490 && MBBI->getOperand(1).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
491 && MBBI->getOperand(2).getReg() == SP::G0); in tryCombineRestoreWithPrevInst()
DSparcFrameLowering.cpp230 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
231 .addReg(SP::G0); in emitEpilogue()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td138 // t<cond> %icc, rs => t<cond> %icc, G0 + rs
140 (TICCrr G0, IntRegs:$rs2, condVal)>,
148 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
150 (TXCCrr G0, IntRegs:$rs2, condVal)>,
158 // t<cond> rs=> t<cond> %icc, G0 + rs2
160 // (TICCrr G0, IntRegs:$rs2, condVal)>,
168 // t<cond> %icc, imm => t<cond> %icc, G0 + imm
170 (TICCri G0, i32imm:$imm, condVal)>,
176 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
178 (TXCCri G0, i32imm:$imm, condVal)>,
[all …]
DDelaySlotFiller.cpp417 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
418 && OrMI->getOperand(2).getReg() != SP::G0) in combineRestoreOR()
422 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
489 && MBBI->getOperand(0).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
490 && MBBI->getOperand(1).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
491 && MBBI->getOperand(2).getReg() == SP::G0); in tryCombineRestoreWithPrevInst()
DSparcFrameLowering.cpp229 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
230 .addReg(SP::G0); in emitEpilogue()
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td139 // t<cond> %icc, rs => t<cond> %icc, G0 + rs
141 (TICCrr G0, IntRegs:$rs2, condVal)>,
149 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
151 (TXCCrr G0, IntRegs:$rs2, condVal)>,
159 // t<cond> rs=> t<cond> %icc, G0 + rs2
161 // (TICCrr G0, IntRegs:$rs2, condVal)>,
169 // t<cond> %icc, imm => t<cond> %icc, G0 + imm
171 (TICCri G0, i32imm:$imm, condVal)>,
177 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
179 (TXCCri G0, i32imm:$imm, condVal)>,
[all …]
DDelaySlotFiller.cpp420 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
421 && OrMI->getOperand(2).getReg() != SP::G0) in combineRestoreOR()
425 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
473 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
492 && MBBI->getOperand(0).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
493 && MBBI->getOperand(1).getReg() == SP::G0 in tryCombineRestoreWithPrevInst()
494 && MBBI->getOperand(2).getReg() == SP::G0); in tryCombineRestoreWithPrevInst()
DSparcFrameLowering.cpp212 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
213 .addReg(SP::G0); in emitEpilogue()
/external/llvm-project/flang/test/Semantics/
Dio07.f9075 8001 format(9G0.5)
78 8101 format(9(G0.5e1))
81 8102 format(9(G0.5 E 1))
/external/webp/src/dsp/
Dyuv_sse41.c51 const __m128i G0 = _mm_mulhi_epu16(*U0, k6419); in ConvertYUV444ToRGB_SSE41() local
54 const __m128i G3 = _mm_add_epi16(G0, G1); in ConvertYUV444ToRGB_SSE41()
135 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in VP8YuvToRgb32_SSE41() local
138 YUV444ToRGB_SSE41(y + 0, u + 0, v + 0, &R0, &G0, &B0); in VP8YuvToRgb32_SSE41()
146 rgb2 = _mm_packus_epi16(G0, G1); in VP8YuvToRgb32_SSE41()
157 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in VP8YuvToBgr32_SSE41() local
160 YUV444ToRGB_SSE41(y + 0, u + 0, v + 0, &R0, &G0, &B0); in VP8YuvToBgr32_SSE41()
168 bgr2 = _mm_packus_epi16(G0, G1); in VP8YuvToBgr32_SSE41()
185 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in YuvToRgbRow_SSE41() local
188 YUV420ToRGB_SSE41(y + 0, u + 0, v + 0, &R0, &G0, &B0); in YuvToRgbRow_SSE41()
[all …]
Dyuv_sse2.c51 const __m128i G0 = _mm_mulhi_epu16(*U0, k6419); in ConvertYUV444ToRGB_SSE2() local
54 const __m128i G3 = _mm_add_epi16(G0, G1); in ConvertYUV444ToRGB_SSE2()
249 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in VP8YuvToRgb32_SSE2() local
252 YUV444ToRGB_SSE2(y + 0, u + 0, v + 0, &R0, &G0, &B0); in VP8YuvToRgb32_SSE2()
260 rgb2 = _mm_packus_epi16(G0, G1); in VP8YuvToRgb32_SSE2()
271 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in VP8YuvToBgr32_SSE2() local
274 YUV444ToRGB_SSE2(y + 0, u + 0, v + 0, &R0, &G0, &B0); in VP8YuvToBgr32_SSE2()
282 bgr2 = _mm_packus_epi16(G0, G1); in VP8YuvToBgr32_SSE2()
365 __m128i R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3; in YuvToRgbRow_SSE2() local
368 YUV420ToRGB_SSE2(y + 0, u + 0, v + 0, &R0, &G0, &B0); in YuvToRgbRow_SSE2()
[all …]
Dcommon_sse41.h42 __m128i G0, G1, G2, G3, G4, G5; in VP8PlanarTo24b_SSE41() local
82 const __m128i RG0 = _mm_or_si128(R0, G0); in VP8PlanarTo24b_SSE41()
/external/llvm-project/llvm/test/CodeGen/X86/
Dattribute-sections.ll4 @G0 = global i32 ()* @foo, section ".init_array"
7 ; LINUX: .globl G0
/external/llvm/test/CodeGen/X86/
Dattribute-sections.ll4 @G0 = global i32 ()* @foo, section ".init_array"
7 ; LINUX: .globl G0
/external/llvm-project/llvm/unittests/IR/
DValueTest.cpp140 GlobalVariable *G0 = M->getGlobalVariable("g0"); in TEST() local
141 ASSERT_TRUE(G0); in TEST()
185 CHECK_PRINT_AS_OPERAND(G0, true, "%0* @g0"); in TEST()
/external/llvm-project/llvm/test/Transforms/GlobalOpt/
Dmemset.ll7 @G0 = internal global [58 x i8] c"asdlfkajsdlfkajsd;lfkajds;lfkjasd;flkajsd;lkfja;sdlkfjasd\00" …
14 …call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @G0, i32 0, i32 …
/external/llvm/test/Transforms/GlobalOpt/
Dmemset.ll7 @G0 = internal global [58 x i8] c"asdlfkajsdlfkajsd;lfkajds;lfkjasd;flkajsd;lkfja;sdlkfjasd\00" …
14 …call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @G0, i32 0, i32 …
/external/llvm-project/lld/test/ELF/
Daarch64-movw-tprel.s14 ## offset from the thread pointer TP. The G0, G1 and G2 refer to partitions
15 ## of the result with G2 bits [47:32], G1 bits [31:16] and G0 bits [15:0]
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp67 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
153 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/external/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcInstPrinter.cpp68 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
154 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcInstPrinter.cpp67 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
153 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dfloat-const64-G0.ll3 ; Check that no CONST64's are emitted for a -G0, mv5 compile

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