1 #ifndef GEN8_MEDIA_H
2 #define GEN8_MEDIA_H
3 
4 #include <stdint.h>
5 #include "surfaceformat.h"
6 
7 #define GEN8_FLOATING_POINT_IEEE_754		0
8 #define GEN8_FLOATING_POINT_NON_IEEE_754	1
9 
10 #define GFXPIPE(Pipeline,Opcode,Subopcode) ((3 << 29) |			\
11 						((Pipeline) << 27) |	\
12 						((Opcode) << 24) |	\
13 						((Subopcode) << 16))
14 
15 #define GEN8_PIPELINE_SELECT			GFXPIPE(1, 1, 4)
16 # define PIPELINE_SELECT_3D			(0 << 0)
17 # define PIPELINE_SELECT_MEDIA			(1 << 0)
18 
19 #define GEN8_STATE_BASE_ADDRESS			GFXPIPE(0, 1, 1)
20 # define BASE_ADDRESS_MODIFY			(1 << 0)
21 
22 #define GEN8_MEDIA_VFE_STATE			GFXPIPE(2, 0, 0)
23 #define GEN8_MEDIA_CURBE_LOAD			GFXPIPE(2, 0, 1)
24 #define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD	GFXPIPE(2, 0, 2)
25 #define GEN8_MEDIA_STATE_FLUSH			GFXPIPE(2, 0, 4)
26 #define GEN8_MEDIA_OBJECT			GFXPIPE(2, 1, 0)
27 
28 struct gen8_interface_descriptor_data
29 {
30 	struct {
31 		uint32_t pad0:6;
32 		uint32_t kernel_start_pointer:26;
33 	} desc0;
34 
35 	struct {
36 		uint32_t kernel_start_pointer_high:16;
37 		uint32_t pad0:16;
38 	} desc1;
39 
40 	struct {
41 		uint32_t pad0:7;
42 		uint32_t software_exception_enable:1;
43 		uint32_t pad1:3;
44 		uint32_t maskstack_exception_enable:1;
45 		uint32_t pad2:1;
46 		uint32_t illegal_opcode_exception_enable:1;
47 		uint32_t pad3:2;
48 		uint32_t floating_point_mode:1;
49 		uint32_t thread_priority:1;
50 		uint32_t single_program_flow:1;
51 		uint32_t denorm_mode:1;
52 		uint32_t pad4:12;
53 	} desc2;
54 
55 	struct {
56 		uint32_t pad0:2;
57 		uint32_t sampler_count:3;
58 		uint32_t sampler_state_pointer:27;
59 	} desc3;
60 
61 	struct {
62 		uint32_t binding_table_entry_count:5;
63 		uint32_t binding_table_pointer:11;
64 		uint32_t pad0: 16;
65 	} desc4;
66 
67 	struct {
68 		uint32_t constant_urb_entry_read_offset:16;
69 		uint32_t constant_urb_entry_read_length:16;
70 	} desc5;
71 
72 	struct {
73 		uint32_t num_threads_in_tg:10;
74 		uint32_t pad0:5;
75 		uint32_t global_barrier_enable:1;
76 		uint32_t shared_local_memory_size:5;
77 		uint32_t barrier_enable:1;
78 		uint32_t rounding_mode:2;
79 		uint32_t pad1:8;
80 	} desc6;
81 
82 	struct {
83 		uint32_t cross_thread_constant_data_read_length:8;
84 		uint32_t pad0:24;
85 	} desc7;
86 };
87 
88 struct gen8_surface_state
89 {
90 	struct {
91 		uint32_t cube_pos_z:1;
92 		uint32_t cube_neg_z:1;
93 		uint32_t cube_pos_y:1;
94 		uint32_t cube_neg_y:1;
95 		uint32_t cube_pos_x:1;
96 		uint32_t cube_neg_x:1;
97 		uint32_t media_boundary_pixel_mode:2;
98 		uint32_t render_cache_read_write:1;
99 		uint32_t sampler_l2_bypass_disable:1;
100 		uint32_t vert_line_stride_ofs:1;
101 		uint32_t vert_line_stride:1;
102 		uint32_t tiled_mode:2;
103 		uint32_t horizontal_alignment:2;
104 		uint32_t vertical_alignment:2;
105 		uint32_t surface_format:9;     /**< BRW_SURFACEFORMAT_x */
106 		uint32_t pad0:1;
107 		uint32_t is_array:1;
108 		uint32_t surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
109 	} ss0;
110 
111 	struct {
112 		uint32_t qpitch:15;
113 		uint32_t pad1:4;
114 		uint32_t base_mip_level:5;
115 		uint32_t memory_object_control:7;
116 		uint32_t pad0:1;
117 	} ss1;
118 
119 	struct {
120 		uint32_t width:14;
121 		uint32_t pad1:2;
122 		uint32_t height:14;
123 		uint32_t pad0:2;
124 	} ss2;
125 
126 	struct {
127 		uint32_t pitch:18;
128 		uint32_t pad:3;
129 		uint32_t depth:11;
130 	} ss3;
131 
132 	struct {
133 		uint32_t multisample_position_palette_index:3;
134 		uint32_t num_multisamples:3;
135 		uint32_t multisampled_surface_storage_format:1;
136 		uint32_t render_target_view_extent:11;
137 		uint32_t min_array_elt:11;
138 		uint32_t rotation:2;
139 		uint32_t force_ncmp_reduce_type:1;
140 	} ss4;
141 
142 	struct {
143 		uint32_t mip_count:4;
144 		uint32_t min_lod:4;
145 		uint32_t pad3:6;
146 		uint32_t coherency_type:1;
147 		uint32_t pad2:5;
148 		uint32_t ewa_disable_for_cube:1;
149 		uint32_t y_offset:3;
150 		uint32_t pad0:1;
151 		uint32_t x_offset:7;
152 	} ss5;
153 
154 	struct {
155 		uint32_t pad; /* Multisample Control Surface stuff */
156 	} ss6;
157 
158 	struct {
159 		uint32_t resource_min_lod:12;
160 
161 		/* Only on Haswell */
162 		uint32_t pad0:4;
163 		uint32_t shader_chanel_select_a:3;
164 		uint32_t shader_chanel_select_b:3;
165 		uint32_t shader_chanel_select_g:3;
166 		uint32_t shader_chanel_select_r:3;
167 
168 		uint32_t alpha_clear_color:1;
169 		uint32_t blue_clear_color:1;
170 		uint32_t green_clear_color:1;
171 		uint32_t red_clear_color:1;
172 	} ss7;
173 
174 	struct {
175 		uint32_t base_addr;
176 	} ss8;
177 
178 	struct {
179 		uint32_t base_addr_hi:16;
180 		uint32_t pad0:16;
181 	} ss9;
182 
183 	struct {
184 		uint32_t pad0:12;
185 		uint32_t aux_base_addr:20;
186 	} ss10;
187 
188 	struct {
189 		uint32_t aux_base_addr_hi:16;
190 		uint32_t pad:16;
191 	} ss11;
192 
193 	struct {
194 		uint32_t hiz_depth_clear_value;
195 	} ss12;
196 
197 	struct {
198 		uint32_t reserved;
199 	} ss13;
200 
201 	struct {
202 		uint32_t reserved;
203 	} ss14;
204 
205 	struct {
206 		uint32_t reserved;
207 	} ss15;
208 };
209 
210 
211 #define GEN9_PIPELINE_SELECTION_MASK		(3 << 8)
212 
213 /*  If enabled, it will force awake media enginee and the following instructions
214  *  will require that the media enginee is awake.
215  */
216 #define GEN9_FORCE_MEDIA_AWAKE_DISABLE		(0 << 5)
217 #define GEN9_FORCE_MEDIA_AWAKE_ENABLE		(1 << 5)
218 #define GEN9_FORCE_MEDIA_AWAKE_MASK		(1 << 13)
219 
220 #define GEN9_SAMPLER_DOP_GATE_DISABLE		(0 << 4)
221 #define GEN9_SAMPLER_DOP_GATE_ENABLE		(1 << 4)
222 #define GEN9_SAMPLER_DOP_GATE_MASK		(1 << 12)
223 
224 #endif /* GEN8_MEDIA_H */
225