| /external/rust/crates/gdbstub/src/arch/mips/reg/ |
| D | id.rs | 32 Hi2, enumerator
61 74 => MipsRegId::Hi2, in from_raw_id()
|
| /external/llvm-project/clang/test/SemaCXX/ |
| D | warn-bitfield-enum-conversion.cpp | 5 enum TwoBitsSigned { Lo2 = -2, Hi2 = 1 } two_bits_signed; enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 752 SDValue Hi2 = Node->getOperand(3); in trySelect() local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 752 SDValue Hi2 = Node->getOperand(3); in trySelect() local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 345 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
356 .add(Hi2); in selectG_ADD_SUB()
368 .add(Hi2) in selectG_ADD_SUB()
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| D | SIISelLowering.cpp | 4021 SDValue Lo2, Hi2; in splitTernaryVectorOp() local
4022 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2); in splitTernaryVectorOp()
4028 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2, in splitTernaryVectorOp()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 355 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
366 .add(Hi2); in selectG_ADD_SUB()
378 .add(Hi2) in selectG_ADD_SUB()
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| D | SIISelLowering.cpp | 4502 SDValue Lo2, Hi2; in splitTernaryVectorOp() local
4503 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2); in splitTernaryVectorOp()
4509 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2, in splitTernaryVectorOp()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 4981 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
5003 (AND Shift2.Left, MaskValues.Hi2));
5046 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32));
5055 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC);
5064 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2));
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 5182 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
5204 (AND Shift2.Left, MaskValues.Hi2));
5250 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32));
5259 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC);
5268 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2));
|