| /external/python/cpython2/Modules/ |
| D | fcntlmodule.c | 436 #define INS(x) if (ins(d, #x, (long)x)) return -1 macro
570 INS(I_PUSH); in all_ins()
571 INS(I_POP); in all_ins()
572 INS(I_LOOK); in all_ins()
573 INS(I_FLUSH); in all_ins()
574 INS(I_FLUSHBAND); in all_ins()
575 INS(I_SETSIG); in all_ins()
576 INS(I_GETSIG); in all_ins()
577 INS(I_FIND); in all_ins()
578 INS(I_PEEK); in all_ins()
[all …]
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | inselt-binop.ll | 6 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 0
7 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
17 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 0
18 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
30 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 1
31 ; CHECK-NEXT: [[BO:%.*]] = sub nuw nsw <2 x i8> <i8 undef, i8 -42>, [[INS]]
41 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 1
42 ; CHECK-NEXT: [[BO:%.*]] = sub nuw <2 x i8> <i8 42, i8 -42>, [[INS]]
52 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 0
53 ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 undef>
[all …]
|
| D | insert-const-shuf.ll | 8 ; CHECK-NEXT: [[INS:%.*]] = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.0000…
9 ; CHECK-NEXT: ret <4 x float> [[INS]]
43 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 0
44 ; CHECK-NEXT: ret <4 x float> [[INS]]
56 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3
57 ; CHECK-NEXT: ret <4 x float> [[INS]]
69 ; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3
70 ; CHECK-NEXT: ret <4 x float> [[INS]]
83 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x float> [[SHUF]], float 4.200000e+01, i2 1
84 ; CHECK-NEXT: [[ADD:%.*]] = fadd <3 x float> [[SHUF]], [[INS]]
[all …]
|
| /external/XNNPACK/src/f32-igemm/ |
| D | 1x12-minmax-aarch64-neonfma-cortex-a53.S | 97 INS v2.d[1], x14
111 INS v3.d[1], x15
116 INS v4.d[1], x16
122 INS v5.d[1], x17
129 INS v6.d[1], x13
134 INS v7.d[1], x7
150 INS v23.d[1], x14 // v23 was loaded in block 2
158 INS v24.d[1], x15
162 INS v25.d[1], x16
167 INS v17.d[1], x17
[all …]
|
| D | 4x12-minmax-aarch64-neonfma-cortex-a53.S | 162 # INS is 4 blocks (16 cycles) after load
166 INS v11.d[1], x8
175 INS v2.d[1], x8 // a1 was loaded in block 0
184 INS v3.d[1], x8 // a3 was loaded in block 1
193 INS v14.d[1], x8 // v14 was loaded in block 2
202 INS v15.d[1], x8
211 INS v16.d[1], x8
220 INS v17.d[1], x8
229 INS v18.d[1], x8
240 INS v19.d[1], x8
[all …]
|
| D | 4x8-minmax-aarch64-neonfma-cortex-a55.S | 159 INS v19.d[1], x19 // b from second group
167 INS v3.d[1], x19 // a1 ins
175 INS v12.d[1], x19 // b ins
183 INS v4.d[1], x19 // a3 ins
191 INS v13.d[1], x19 // b
200 INS v14.d[1], x19 // b from previous
209 INS v15.d[1], x19 // b from previous
217 INS v0.d[1], x19 // a1 ins
225 INS v16.d[1], x19 // b
233 INS v1.d[1], x19 // a3 ins
[all …]
|
| D | 4x8-minmax-aarch64-neonfma-cortex-a53.S | 157 INS v19.d[1], x19 // b from second group
165 INS v3.d[1], x19 // a1 ins
173 INS v12.d[1], x19 // b ins
181 INS v4.d[1], x19 // a3 ins
189 INS v13.d[1], x19 // b
198 INS v14.d[1], x19 // b from previous
209 INS v15.d[1], x19 // b from previous
218 INS v0.d[1], x19 // a1 ins
227 INS v16.d[1], x19 // b
236 INS v1.d[1], x19 // a3 ins
[all …]
|
| D | 6x8-minmax-aarch64-neonfma-cortex-a55.S | 175 INS v19.d[1], x19 // b from second group
183 INS v3.d[1], x19 // a1 ins
191 INS v12.d[1], x19 // b ins
199 INS v4.d[1], x19 // a3 ins
207 INS v5.d[1], x19 // a5 ins
215 INS v13.d[1], x19 // b
223 INS v14.d[1], x19 // b
230 INS v15.d[1], x19
245 INS v0.d[1], x19 // a1 ins
253 INS v16.d[1], x19 // b
[all …]
|
| D | 6x8-minmax-aarch64-neonfma-cortex-a53.S | 171 INS v19.d[1], x19 // b from second group
179 INS v3.d[1], x19 // a1 ins
187 INS v12.d[1], x19 // b ins
195 INS v4.d[1], x19 // a3 ins
203 INS v5.d[1], x19 // a5 ins
211 INS v13.d[1], x19 // b
219 INS v14.d[1], x19 // b
226 INS v15.d[1], x19
242 INS v0.d[1], x19 // a1 ins
251 INS v16.d[1], x19 // b
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign.ll | 19 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
20 ; 32R2: mthc1 $[[INS]], $f0
31 ; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
32 ; 64R2: dmtc1 $[[INS]], $f0
52 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
53 ; 32R2: mtc1 $[[INS]], $f0
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | fcopysign.ll | 24 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
25 ; 32R2: mthc1 $[[INS]], $f0
36 ; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1
37 ; 64R2: dmtc1 $[[INS]], $f0
57 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
58 ; 32R2: mtc1 $[[INS]], $f0
|
| D | fcopysign-f32-f64.ll | 26 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
27 ; 64R2: mtc1 $[[INS]], $f0
51 ; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
52 ; 64R2: dmtc1 $[[INS]], $f0
|
| /external/XNNPACK/src/f32-gemm/gen/ |
| D | 4x12-minmax-aarch64-neonfma-cortex-a53.S | 143 # INS is 4 blocks (16 cycles) after load
147 INS v11.d[1], x8
156 INS v2.d[1], x8 // a1 was loaded in block 0
165 INS v3.d[1], x8 // a3 was loaded in block 1
174 INS v14.d[1], x8 // v14 was loaded in block 2
183 INS v15.d[1], x8
192 INS v16.d[1], x8
201 INS v17.d[1], x8
210 INS v18.d[1], x8
221 INS v19.d[1], x8
[all …]
|
| D | 4x8-minmax-aarch64-neonfma-cortex-a53.S | 140 INS v19.d[1], x4 // b from second group
148 INS v3.d[1], x4 // a1 ins
156 INS v12.d[1], x4 // b ins
164 INS v4.d[1], x4 // a3 ins
172 INS v13.d[1], x4 // b
181 INS v14.d[1], x4 // b from previous
192 INS v15.d[1], x4 // b from previous
201 INS v0.d[1], x4 // a1 ins
210 INS v16.d[1], x4 // b
219 INS v1.d[1], x4 // a3 ins
[all …]
|
| D | 4x8-minmax-aarch64-neonfma-cortex-a55.S | 142 INS v19.d[1], x4 // b from second group
150 INS v3.d[1], x4 // a1 ins
158 INS v12.d[1], x4 // b ins
166 INS v4.d[1], x4 // a3 ins
174 INS v13.d[1], x4 // b
183 INS v14.d[1], x4 // b from previous
192 INS v15.d[1], x4 // b from previous
200 INS v0.d[1], x4 // a1 ins
208 INS v16.d[1], x4 // b
216 INS v1.d[1], x4 // a3 ins
[all …]
|
| D | 6x8-minmax-aarch64-neonfma-cortex-a55.S | 165 INS v19.d[1], x8 // b from second group
173 INS v3.d[1], x8 // a1 ins
181 INS v12.d[1], x8 // b ins
189 INS v4.d[1], x8 // a3 ins
197 INS v5.d[1], x8 // a5 ins
205 INS v13.d[1], x8 // b
213 INS v14.d[1], x8 // b
220 INS v15.d[1], x8
235 INS v0.d[1], x8 // a1 ins
243 INS v16.d[1], x8 // b
[all …]
|
| D | 6x8-minmax-aarch64-neonfma-cortex-a53.S | 161 INS v19.d[1], x8 // b from second group
169 INS v3.d[1], x8 // a1 ins
177 INS v12.d[1], x8 // b ins
185 INS v4.d[1], x8 // a3 ins
193 INS v5.d[1], x8 // a5 ins
201 INS v13.d[1], x8 // b
209 INS v14.d[1], x8 // b
216 INS v15.d[1], x8
232 INS v0.d[1], x8 // a1 ins
241 INS v16.d[1], x8 // b
[all …]
|
| /external/XNNPACK/src/f32-gemm/gen-inc/ |
| D | 4x12inc-minmax-aarch64-neonfma-cortex-a53.S | 140 # INS is 4 blocks (16 cycles) after load
144 INS v11.d[1], x8
153 INS v2.d[1], x8 // a1 was loaded in block 0
162 INS v3.d[1], x8 // a3 was loaded in block 1
171 INS v14.d[1], x8 // v14 was loaded in block 2
180 INS v15.d[1], x8
189 INS v16.d[1], x8
198 INS v17.d[1], x8
207 INS v18.d[1], x8
218 INS v19.d[1], x8
[all …]
|
| D | 4x8inc-minmax-aarch64-neonfma-cortex-a53.S | 138 INS v19.d[1], x4 // b from second group
146 INS v3.d[1], x4 // a1 ins
154 INS v12.d[1], x4 // b ins
162 INS v4.d[1], x4 // a3 ins
170 INS v13.d[1], x4 // b
179 INS v14.d[1], x4 // b from previous
190 INS v15.d[1], x4 // b from previous
199 INS v0.d[1], x4 // a1 ins
208 INS v16.d[1], x4 // b
217 INS v1.d[1], x4 // a3 ins
[all …]
|
| D | 4x8inc-minmax-aarch64-neonfma-cortex-a55.S | 140 INS v19.d[1], x4 // b from second group
148 INS v3.d[1], x4 // a1 ins
156 INS v12.d[1], x4 // b ins
164 INS v4.d[1], x4 // a3 ins
172 INS v13.d[1], x4 // b
181 INS v14.d[1], x4 // b from previous
190 INS v15.d[1], x4 // b from previous
198 INS v0.d[1], x4 // a1 ins
206 INS v16.d[1], x4 // b
214 INS v1.d[1], x4 // a3 ins
[all …]
|
| D | 6x8inc-minmax-aarch64-neonfma-cortex-a53.S | 157 INS v19.d[1], x8 // b from second group
165 INS v3.d[1], x8 // a1 ins
173 INS v12.d[1], x8 // b ins
181 INS v4.d[1], x8 // a3 ins
189 INS v5.d[1], x8 // a5 ins
197 INS v13.d[1], x8 // b
205 INS v14.d[1], x8 // b
212 INS v15.d[1], x8
228 INS v0.d[1], x8 // a1 ins
237 INS v16.d[1], x8 // b
[all …]
|
| D | 6x8inc-minmax-aarch64-neonfma-cortex-a55.S | 161 INS v19.d[1], x8 // b from second group
169 INS v3.d[1], x8 // a1 ins
177 INS v12.d[1], x8 // b ins
185 INS v4.d[1], x8 // a3 ins
193 INS v5.d[1], x8 // a5 ins
201 INS v13.d[1], x8 // b
209 INS v14.d[1], x8 // b
216 INS v15.d[1], x8
231 INS v0.d[1], x8 // a1 ins
239 INS v16.d[1], x8 // b
[all …]
|
| /external/XNNPACK/src/qs8-igemm/ |
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 117 # 4 LD128 for W. = 2 LD64 + INS.
118 # for each 4 sdot, 1 LD64 for A, 2 LD64 for W + INS.
126 INS v9.d[1], x14
136 INS v10.d[1], x14
146 INS v11.d[1], x14
156 INS v8.d[1], x14
166 INS v9.d[1], x14
175 INS v10.d[1], x14
184 INS v11.d[1], x14
193 INS v8.d[1], x14
[all …]
|
| /external/XNNPACK/src/qs8-gemm/ |
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 96 # 4 LD128 for W. = 2 LD64 + INS.
97 # for each 4 sdot, 1 LD64 for A, 2 LD64 for W + INS.
105 INS v9.d[1], x14
115 INS v10.d[1], x14
125 INS v11.d[1], x14
135 INS v8.d[1], x14
145 INS v9.d[1], x14
154 INS v10.d[1], x14
163 INS v11.d[1], x14
172 INS v8.d[1], x14
[all …]
|
| /external/XNNPACK/src/f32-gemm/ |
| D | 4x12-aarch64-neonfma-cortex-a53.S.in | 170 # INS is 4 blocks (16 cycles) after load
174 INS v11.d[1], x8
183 INS v2.d[1], x8 // a1 was loaded in block 0
192 INS v3.d[1], x8 // a3 was loaded in block 1
201 INS v14.d[1], x8 // v14 was loaded in block 2
210 INS v15.d[1], x8
219 INS v16.d[1], x8
228 INS v17.d[1], x8
237 INS v18.d[1], x8
248 INS v19.d[1], x8
[all …]
|