| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 80 Register InReg = PPC::NoRegister; in processBlock() local
84 InReg = MI.getOperand(1).getReg(); in processBlock()
85 OrigRegs.push_back(InReg); in processBlock()
133 assert(InReg != PPC::NoRegister && "Operand must be a register"); in processBlock()
134 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); in processBlock()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 72 unsigned InReg = MI->getOperand(1).getReg(); in processBlock() local
76 const unsigned OrigRegs[] = {OutReg, InReg, GPR3}; in processBlock()
106 .addReg(InReg); in processBlock()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 79 Register InReg = MI.getOperand(1).getReg(); in processBlock() local
83 const unsigned OrigRegs[] = {OutReg, InReg, GPR3}; in processBlock()
118 .addReg(InReg); in processBlock()
|
| /external/clang/include/clang/CodeGen/ |
| D | CGFunctionInfo.h | 96 bool InReg : 1; // isDirect() || isExtend() || isIndirect() variable
113 : TheKind(K), PaddingInReg(false), InReg(false) { in ABIArgInfo()
119 TheKind(Direct), PaddingInReg(false), InReg(false) {} in ABIArgInfo()
300 return InReg; in getInReg()
305 InReg = IR; in setInReg()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 32 static const uint64_t InReg = 1ULL<<2; ///< Passed in register member
76 bool isInReg() const { return Flags & InReg; } in isInReg()
|
| /external/llvm-project/clang/include/clang/CodeGen/ |
| D | CGFunctionInfo.h | 109 bool InReg : 1; // isDirect() || isExtend() || isIndirect() variable
132 SRetAfterThis(false), InReg(false), CanBeFlattened(false), in TypeData()
361 return InReg; in getInReg()
366 InReg = IR; in setInReg()
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-windows-calls.ll | 73 ; InReg arguments to non-instance methods must be passed in X0 and returns in
86 ; InReg arguments to instance methods must be passed in X1 and returns in X0.
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| D | Attributes.inc | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 614 const bool InReg = Arg.hasAttribute(Attribute::InReg); in lowerFormalArguments() local
617 if (!IsShader && InReg) in lowerFormalArguments()
625 if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) { in lowerFormalArguments()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 104 IsInReg = Call.paramHasAttr(0, Attribute::InReg); in setCallee()
128 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 110 IsInReg = Call.hasRetAttr(Attribute::InReg); in setCallee()
134 IsInReg = Call.hasRetAttr(Attribute::InReg);
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 109 IsInReg = Call.hasRetAttr(Attribute::InReg); in setCallee()
133 IsInReg = Call.hasRetAttr(Attribute::InReg);
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | Attributes.inc | 15 InReg,
84 .Case("inreg", Attribute::InReg)
233 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/IR/ |
| D | AttributesCompatFunc.inc | 15 InReg,
84 .Case("inreg", Attribute::InReg)
233 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 352 Register InReg = MI.getOperand(1).getReg(); in LowerFPToInt() local
388 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
389 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
399 Tmp0 = InReg; in LowerFPToInt()
401 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
409 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
425 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 342 Register InReg = MI.getOperand(1).getReg(); in LowerFPToInt() local
378 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
379 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
389 Tmp0 = InReg; in LowerFPToInt()
391 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
399 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
415 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 297 if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) || in isArgPassedInSGPR()
|
| /external/mesa3d/src/amd/llvm/ |
| D | ac_llvm_helper.cpp | 69 return AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg); in ac_is_sgpr_param()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 826 const bool InReg = Arg.hasAttribute(Attribute::InReg); in lowerFormalArguments() local
829 if (!IsGraphics && InReg) in lowerFormalArguments()
837 if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) { in lowerFormalArguments()
|
| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 924 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1430 bool &InReg, in shouldAggregateUseDirect() argument
1439 InReg = !IsMCUABI; in shouldAggregateUseDirect()
1523 bool InReg; in classifyArgumentType() local
1524 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) { in classifyArgumentType()
1528 if (InReg) in classifyArgumentType()
1572 bool InReg = shouldPrimitiveUseInReg(Ty, State); in classifyArgumentType() local
1575 if (InReg) in classifyArgumentType()
1580 if (InReg) in classifyArgumentType()
6852 bool InReg = shouldUseInReg(Ty, State); in classifyArgumentType() local
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