| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | GPRArith.cpp | 678 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
684 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 ", " #Src0 \ in TEST_F()
696 __ Inst1(IceType_i##Size, GPRRegister::Encoded_Reg_##Dst1, \ in TEST_F()
711 #define TestImplRegAddr(Inst0, Inst1, Dst0, Dst1, Value0, Value1, Op, Size) \ in TEST_F() argument
716 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
728 __ Inst1(IceType_i##Size, GPRRegister::Encoded_Reg_##Dst1, \ in TEST_F()
745 #define TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Imm, Op, Size) \ in TEST_F() argument
750 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
758 __ Inst1(IceType_i##Size, GPRRegister::Encoded_Reg_##Dst1, \ in TEST_F()
773 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | GPRArith.cpp | 709 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
715 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 ", " #Src0 \ in TEST_F()
726 __ Inst1(IceType_i##Size, Encoded_GPR_##Dst1(), Encoded_GPR_##Src1()); \ in TEST_F()
740 #define TestImplRegAddr(Inst0, Inst1, Dst0, Dst1, Value0, Value1, Op, Size) \ in TEST_F() argument
745 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
756 __ Inst1(IceType_i##Size, Encoded_GPR_##Dst1(), dwordAddress(T1)); \ in TEST_F()
772 #define TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Imm, Op, Size) \ in TEST_F() argument
777 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 \ in TEST_F()
785 __ Inst1(IceType_i##Size, Encoded_GPR_##Dst1(), \ in TEST_F()
800 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
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| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.cpp | 539 MCInst const &Inst1 = *ID.getOperand(1).getInst(); in GetPacketSummary() local
542 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) in GetPacketSummary()
546 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) in GetPacketSummary()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.cpp | 401 MCInst const &Inst1 = *ID.getOperand(1).getInst(); in check() local
404 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) in check()
408 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) in check()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 548 MDNode *llvm::intersectAccessGroups(const Instruction *Inst1, in intersectAccessGroups() argument
550 bool MayAccessMem1 = Inst1->mayReadOrWriteMemory(); in intersectAccessGroups()
558 return Inst1->getMetadata(LLVMContext::MD_access_group); in intersectAccessGroups()
560 MDNode *MD1 = Inst1->getMetadata(LLVMContext::MD_access_group); in intersectAccessGroups()
590 LLVMContext &Ctx = Inst1->getContext(); in intersectAccessGroups()
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| /external/llvm-project/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 662 MDNode *llvm::intersectAccessGroups(const Instruction *Inst1, in intersectAccessGroups() argument
664 bool MayAccessMem1 = Inst1->mayReadOrWriteMemory(); in intersectAccessGroups()
672 return Inst1->getMetadata(LLVMContext::MD_access_group); in intersectAccessGroups()
674 MDNode *MD1 = Inst1->getMetadata(LLVMContext::MD_access_group); in intersectAccessGroups()
704 LLVMContext &Ctx = Inst1->getContext(); in intersectAccessGroups()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.h | 79 const SUnit &Inst1, const SUnit &Inst2) const;
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| D | HexagonSubtarget.cpp | 181 const HexagonInstrInfo &HII, const SUnit &Inst1, in shouldTFRICallBind() argument
183 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.h | 83 const SUnit &Inst1, const SUnit &Inst2) const;
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| D | HexagonSubtarget.cpp | 251 const HexagonInstrInfo &HII, const SUnit &Inst1, in shouldTFRICallBind() argument
253 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
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| /external/llvm/unittests/IR/ |
| D | InstructionsTest.cpp | 284 auto Inst1 = CastInst::CreatePointerCast(NullV2I32Ptr, V2Int32Ty, "foo", BB); in TEST() local
290 Inst1->eraseFromParent(); in TEST()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 283 MDNode *intersectAccessGroups(const Instruction *Inst1,
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| /external/llvm-project/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 454 MDNode *intersectAccessGroups(const Instruction *Inst1,
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| /external/llvm-project/llvm/unittests/IR/ |
| D | InstructionsTest.cpp | 369 auto Inst1 = CastInst::CreatePointerCast(NullV2I32Ptr, V2Int32Ty, "foo", BB); in TEST() local
382 Inst1->eraseFromParent(); in TEST()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 509 bool isAliased(const MemoryLocation &Loc1, Instruction *Inst1, in isAliased() argument
513 AliasCacheKey key = std::make_pair(Inst1, Inst2); in isAliased()
520 if (Loc1.Ptr && Loc2.Ptr && isSimple(Inst1) && isSimple(Inst2)) { in isAliased()
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| /external/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 1953 static bool hasDataDependence(SUnit *Inst1, SUnit *Inst2) { in hasDataDependence() argument
1954 for (auto &SI : Inst1->Succs) in hasDataDependence()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 1731 bool isAliased(const MemoryLocation &Loc1, Instruction *Inst1, in isAliased() argument
1734 AliasCacheKey key = std::make_pair(Inst1, Inst2); in isAliased()
1741 if (Loc1.Ptr && Loc2.Ptr && isSimple(Inst1) && isSimple(Inst2)) { in isAliased()
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| /external/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 1873 bool isAliased(const MemoryLocation &Loc1, Instruction *Inst1, in isAliased() argument
1876 AliasCacheKey key = std::make_pair(Inst1, Inst2); in isAliased()
1883 if (Loc1.Ptr && Loc2.Ptr && isSimple(Inst1) && isSimple(Inst2)) { in isAliased()
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