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Searched refs:IntOp (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2450 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2457 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2465 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2472 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2480 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2483 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td2534 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2537 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2541 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2544 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2549 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2552 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2556 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2559 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2564 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2567 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
DARMISelLowering.cpp14267 unsigned IntOp = cast<ConstantSDNode>(N.getOperand(1))->getZExtValue(); in SearchLoopIntrinsic() local
14268 if (IntOp != Intrinsic::test_set_loop_iterations && in SearchLoopIntrinsic()
14269 IntOp != Intrinsic::loop_decrement_reg) in SearchLoopIntrinsic()
14345 unsigned IntOp = cast<ConstantSDNode>(Int->getOperand(1))->getZExtValue(); in PerformHWLoopCombine() local
14358 if (IntOp == Intrinsic::test_set_loop_iterations) { in PerformHWLoopCombine()
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td2465 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2472 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2480 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2483 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2487 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2490 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2495 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2498 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
[all …]
DARMISelLowering.cpp15903 unsigned IntOp = cast<ConstantSDNode>(N.getOperand(1))->getZExtValue(); in SearchLoopIntrinsic() local
15904 if (IntOp != Intrinsic::test_set_loop_iterations && in SearchLoopIntrinsic()
15905 IntOp != Intrinsic::loop_decrement_reg) in SearchLoopIntrinsic()
15981 unsigned IntOp = cast<ConstantSDNode>(Int->getOperand(1))->getZExtValue(); in PerformHWLoopCombine() local
15994 if (IntOp == Intrinsic::test_set_loop_iterations) { in PerformHWLoopCombine()
/external/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/
DWebAssemblyAsmParser.cpp53 struct IntOp { struct
71 struct IntOp Int;
79 WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) in WebAssemblyOperand()
369 WebAssemblyOperand::IntOp{Val})); in parseSingleInteger()
439 WebAssemblyOperand::IntOp{-1})); in checkForP2AlignIfLoadStore()
456 WebAssemblyOperand::IntOp{static_cast<int64_t>(BT)})); in addBlockTypeOperand()
584 WebAssemblyOperand::IntOp{static_cast<int64_t>(HeapType)})); in ParseInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/AsmParser/
DWebAssemblyAsmParser.cpp51 struct IntOp { struct
69 struct IntOp Int;
77 WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) in WebAssemblyOperand()
349 WebAssemblyOperand::IntOp{Val})); in parseSingleInteger()
413 WebAssemblyOperand::IntOp{-1})); in checkForP2AlignIfLoadStore()
423 WebAssemblyOperand::IntOp{static_cast<int64_t>(BT)})); in addBlockTypeOperand()
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
224 multiclass MATCH_ANY_SYNC<NVPTXRegClass regclass, string ptxtype, Intrinsic IntOp,
228 [(set regclass:$dest, (IntOp imm:$mask, imm:$value))]>,
232 [(set regclass:$dest, (IntOp Int32Regs:$mask, imm:$value))]>,
236 [(set regclass:$dest, (IntOp imm:$mask, regclass:$value))]>,
240 [(set regclass:$dest, (IntOp Int32Regs:$mask, regclass:$value))]>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
224 multiclass MATCH_ANY_SYNC<NVPTXRegClass regclass, string ptxtype, Intrinsic IntOp,
228 [(set regclass:$dest, (IntOp imm:$mask, imm:$value))]>,
232 [(set regclass:$dest, (IntOp Int32Regs:$mask, imm:$value))]>,
236 [(set regclass:$dest, (IntOp imm:$mask, regclass:$value))]>,
240 [(set regclass:$dest, (IntOp Int32Regs:$mask, regclass:$value))]>,
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td69 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
78 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
84 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
90 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
96 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, imm:$mask))]>;
882 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
890 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
898 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
902 string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM, Predicate Pred> {
904 IntOp, IMMType, IMM, Pred>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5233 Intrinsic IntOp> {
5237 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5245 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5253 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5262 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5267 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5272 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5280 Intrinsic IntOp> {
5284 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5297 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td6100 Intrinsic IntOp> {
6104 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6112 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6120 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
6129 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
6134 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
6139 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
6147 Intrinsic IntOp> {
6151 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6164 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td6277 Intrinsic IntOp> {
6281 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6289 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6297 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
6306 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
6311 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
6316 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
6324 Intrinsic IntOp> {
6328 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6341 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
/external/llvm-project/llvm/lib/Analysis/
DScalarEvolution.cpp1138 const SCEV *IntOp = SCEVPtrToIntSinkingRewriter::rewrite(Op, *this); in getPtrToIntExpr() local
1139 assert(IntOp->getType()->isIntegerTy() && in getPtrToIntExpr()
1142 return getTruncateOrZeroExtend(IntOp, Ty); in getPtrToIntExpr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp42732 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp() local
42733 return DAG.getBitcast(VT, IntOp); in lowerX86FPLogicOp()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp46090 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); in lowerX86FPLogicOp() local
46091 return DAG.getBitcast(VT, IntOp); in lowerX86FPLogicOp()