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Searched refs:Is64 (Results 1 – 25 of 32) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Object/
DELFTypes.h47 template <endianness E, bool Is64> struct ELFType {
54 static const bool Is64Bits = Is64;
56 using uint = typename std::conditional<Is64, uint64_t, uint32_t>::type;
57 using Ehdr = Elf_Ehdr_Impl<ELFType<E, Is64>>;
58 using Shdr = Elf_Shdr_Impl<ELFType<E, Is64>>;
59 using Sym = Elf_Sym_Impl<ELFType<E, Is64>>;
60 using Dyn = Elf_Dyn_Impl<ELFType<E, Is64>>;
61 using Phdr = Elf_Phdr_Impl<ELFType<E, Is64>>;
62 using Rel = Elf_Rel_Impl<ELFType<E, Is64>, false>;
63 using Rela = Elf_Rel_Impl<ELFType<E, Is64>, true>;
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/external/llvm-project/llvm/include/llvm/Object/
DELFTypes.h47 template <endianness E, bool Is64> struct ELFType {
54 static const bool Is64Bits = Is64;
56 using uint = std::conditional_t<Is64, uint64_t, uint32_t>;
57 using Ehdr = Elf_Ehdr_Impl<ELFType<E, Is64>>;
58 using Shdr = Elf_Shdr_Impl<ELFType<E, Is64>>;
59 using Sym = Elf_Sym_Impl<ELFType<E, Is64>>;
60 using Dyn = Elf_Dyn_Impl<ELFType<E, Is64>>;
61 using Phdr = Elf_Phdr_Impl<ELFType<E, Is64>>;
62 using Rel = Elf_Rel_Impl<ELFType<E, Is64>, false>;
63 using Rela = Elf_Rel_Impl<ELFType<E, Is64>, true>;
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/external/llvm/include/llvm/Object/
DELFTypes.h39 template <endianness E, bool Is64> struct ELFType {
46 static const bool Is64Bits = Is64;
48 typedef typename std::conditional<Is64, uint64_t, uint32_t>::type uint;
49 typedef Elf_Ehdr_Impl<ELFType<E, Is64>> Ehdr;
50 typedef Elf_Shdr_Impl<ELFType<E, Is64>> Shdr;
51 typedef Elf_Sym_Impl<ELFType<E, Is64>> Sym;
52 typedef Elf_Dyn_Impl<ELFType<E, Is64>> Dyn;
53 typedef Elf_Phdr_Impl<ELFType<E, Is64>> Phdr;
54 typedef Elf_Rel_Impl<ELFType<E, Is64>, false> Rel;
55 typedef Elf_Rel_Impl<ELFType<E, Is64>, true> Rela;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCAsmBackend.cpp210 bool Is64 = TT.isPPC64(); in createObjectTargetWriter() local
212 /*Is64Bit=*/Is64, in createObjectTargetWriter()
213 (Is64 ? MachO::CPU_TYPE_POWERPC64 : MachO::CPU_TYPE_POWERPC), in createObjectTargetWriter()
225 bool Is64 = TT.isPPC64(); in createObjectTargetWriter() local
226 return createPPCELFObjectWriter(Is64, OSABI); in createObjectTargetWriter()
/external/llvm-project/llvm/tools/llvm-objcopy/
DCopyConfig.h43 MachineInfo(uint16_t EM, uint8_t ABI, bool Is64, bool IsLittle) in MachineInfo()
44 : EMachine(EM), OSABI(ABI), Is64Bit(Is64), IsLittleEndian(IsLittle) {} in MachineInfo()
46 MachineInfo(uint16_t EM, bool Is64, bool IsLittle) in MachineInfo()
47 : MachineInfo(EM, ELF::ELFOSABI_NONE, Is64, IsLittle) {} in MachineInfo()
/external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCAsmBackend.cpp222 bool Is64 = TT.isPPC64(); in createObjectTargetWriter() local
223 return createPPCELFObjectWriter(Is64, OSABI); in createObjectTargetWriter()
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsELFObjectWriter.cpp59 MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool Is64);
214 bool HasRelocationAddend, bool Is64) in MipsELFObjectWriter() argument
215 : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) {} in MipsELFObjectWriter()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsELFObjectWriter.cpp59 MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool Is64);
214 bool HasRelocationAddend, bool Is64) in MipsELFObjectWriter() argument
215 : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) {} in MipsELFObjectWriter()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp265 static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) { in getLogicalBitOpcode() argument
268 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32; in getLogicalBitOpcode()
270 return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32; in getLogicalBitOpcode()
272 return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32; in getLogicalBitOpcode()
287 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR() local
289 I.setDesc(TII.get(getLogicalBitOpcode(I.getOpcode(), Is64))); in selectG_AND_OR_XOR()
1095 const bool Is64 = Size == 64; in selectBallot() local
1106 unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32; in selectBallot()
1109 Register SrcReg = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO; in selectBallot()
1664 const bool Is64 = MRI->getType(VDataOut).getSizeInBits() == 64; in selectImageIntrinsic() local
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DAMDGPULegalizerInfo.cpp4536 bool Is64 = MRI.getType(NodePtr).getSizeInBits() == 64; in legalizeBVHIntrinsic() local
4537 unsigned Opcode = IsA16 ? Is64 ? AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa in legalizeBVHIntrinsic()
4539 : Is64 ? AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa in legalizeBVHIntrinsic()
4543 if (Is64) { in legalizeBVHIntrinsic()
/external/llvm-project/llvm/tools/llvm-objcopy/COFF/
DWriter.cpp187 PeHeaderSize = Obj.Is64 ? sizeof(pe32plus_header) : sizeof(pe32_header); in finalize()
280 if (Obj.Is64) { in writeHeaders()
DObject.h103 bool Is64 = false; member
DReader.cpp28 Obj.Is64 = COFFObj.is64(); in readExecutableHeaders()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp238 static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) { in getLogicalBitOpcode() argument
241 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32; in getLogicalBitOpcode()
243 return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32; in getLogicalBitOpcode()
245 return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32; in getLogicalBitOpcode()
1724 const bool Is64 = DstTy.getSizeInBits() == 64; in selectG_EXTRACT_VECTOR_ELT() local
1726 unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0; in selectG_EXTRACT_VECTOR_ELT()
1729 if (DstTy.getSizeInBits() != 32 && !Is64) in selectG_EXTRACT_VECTOR_ELT()
1735 unsigned Opc = Is64 ? AMDGPU::S_MOVRELS_B64 : AMDGPU::S_MOVRELS_B32; in selectG_EXTRACT_VECTOR_ELT()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp1248 bool Is64 = DoubleRegsRegClass.contains(PReg); in getNextPhysReg() local
1249 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); in getNextPhysReg()
1263 if (!Is64) { in getNextPhysReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp1250 bool Is64 = DoubleRegsRegClass.contains(PReg); in getNextPhysReg() local
1251 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); in getNextPhysReg()
1265 if (!Is64) { in getNextPhysReg()
/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp1132 bool Is64 = DoubleRegsRegClass.contains(PReg); in getNextPhysReg() local
1133 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); in getNextPhysReg()
1147 if (!Is64) { in getNextPhysReg()
/external/llvm-project/llvm/tools/llvm-readobj/
DELFDumper.cpp4249 constexpr bool Is64 = ELFT::Is64Bits; in printSectionDetails() local
4251 {Is64 ? "Address" : "Addr", 23}, in printSectionDetails()
4252 {"Off", Is64 ? 40 : 32}, in printSectionDetails()
4253 {"Size", Is64 ? 47 : 39}, in printSectionDetails()
4254 {"ES", Is64 ? 54 : 46}, in printSectionDetails()
4255 {"Lk", Is64 ? 59 : 51}, in printSectionDetails()
4256 {"Inf", Is64 ? 62 : 54}, in printSectionDetails()
4257 {"Al", Is64 ? 66 : 57}}); in printSectionDetails()
4268 const unsigned AddrSize = Is64 ? 16 : 8; in printSectionDetails()
4283 {to_string(format_hex_no_prefix(S.sh_offset, 6)), Is64 ? 39 : 32}, in printSectionDetails()
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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8664Traits.h512 unsigned Is64 : 1;
569 (IntegerRegistersI64)[Entry.Val] = Entry.Is64;
DIceTargetLoweringX8632Traits.h482 unsigned Is64 : 1;
/external/llvm-project/llvm/lib/ObjectYAML/
DELFYAML.cpp1060 const bool Is64 = static_cast<ELFYAML::Object *>(Ctx)->Header.Class == in input() local
1069 const int64_t MinVal = Is64 ? INT64_MIN : INT32_MIN; in input()
1077 const uint64_t MaxVal = Is64 ? UINT64_MAX : UINT32_MAX; in input()
/external/llvm/lib/Object/
DMachOObjectFile.cpp80 bool Is64 = O->is64Bit(); in getSectionPtr() local
81 unsigned SegmentLoadSize = Is64 ? sizeof(MachO::segment_command_64) : in getSectionPtr()
83 unsigned SectionSize = Is64 ? sizeof(MachO::section_64) : in getSectionPtr()
/external/llvm/tools/llvm-readobj/
DELFDumper.cpp1771 bool Is64 = ELFT::Is64Bits; in printDynamicTable() local
1774 << " Tag" << (Is64 ? " " : " ") << "Type" in printDynamicTable()
1780 W.startLine() << " " << format_hex(Tag, Is64 ? 18 : 10, opts::Output != opts::GNU) << " " in printDynamicTable()
2506 static inline void printRelocHeader(raw_ostream &OS, bool Is64, bool IsRela) { in printRelocHeader() argument
2507 if (Is64) in printRelocHeader()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Object/
DMachOObjectFile.cpp98 bool Is64 = O.is64Bit(); in getSectionPtr() local
99 unsigned SegmentLoadSize = Is64 ? sizeof(MachO::segment_command_64) : in getSectionPtr()
101 unsigned SectionSize = Is64 ? sizeof(MachO::section_64) : in getSectionPtr()
/external/llvm-project/llvm/lib/Object/
DMachOObjectFile.cpp98 bool Is64 = O.is64Bit(); in getSectionPtr() local
99 unsigned SegmentLoadSize = Is64 ? sizeof(MachO::segment_command_64) : in getSectionPtr()
101 unsigned SectionSize = Is64 ? sizeof(MachO::section_64) : in getSectionPtr()

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