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Searched refs:IsRV64 (Results 1 – 25 of 32) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Utils/
DRISCVMatInt.cpp19 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { in generateInstSeq() argument
35 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeq()
41 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeq()
71 generateInstSeq(Hi52, IsRV64, Res); in generateInstSeq()
78 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) { in getIntMatCost() argument
79 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
87 generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq); in getIntMatCost()
DRISCVBaseInfo.cpp16 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
23 } else if (ABIName.startswith("ilp32") && IsRV64) { in computeTargetABI()
27 } else if (ABIName.startswith("lp64") && !IsRV64) { in computeTargetABI()
47 if (IsRV64) in computeTargetABI()
DRISCVMatInt.h33 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
41 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64);
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVMatInt.cpp17 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { in generateInstSeq() argument
33 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeq()
39 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeq()
69 generateInstSeq(Hi52, IsRV64, Res); in generateInstSeq()
76 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) { in getIntMatCost() argument
77 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
85 generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq); in getIntMatCost()
DRISCVBaseInfo.cpp29 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
36 } else if (ABIName.startswith("ilp32") && IsRV64) { in computeTargetABI()
40 } else if (ABIName.startswith("lp64") && !IsRV64) { in computeTargetABI()
60 if (IsRV64) in computeTargetABI()
DRISCVMatInt.h32 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
40 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64);
/external/llvm-project/llvm/include/llvm/Support/
DTargetParser.h164 bool checkCPUKind(CPUKind Kind, bool IsRV64);
165 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
167 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
169 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
170 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
172 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
/external/llvm-project/llvm/lib/Support/
DTargetParser.cpp254 bool checkCPUKind(CPUKind Kind, bool IsRV64) { in checkCPUKind() argument
257 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64; in checkCPUKind()
260 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { in checkTuneCPUKind() argument
263 return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64; in checkTuneCPUKind()
273 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) { in resolveTuneCPUAlias() argument
275 #define PROC_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32)) in resolveTuneCPUAlias()
280 CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { in parseTuneCPUKind() argument
281 TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64); in parseTuneCPUKind()
294 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidCPUArchList() argument
296 if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit()) in fillValidCPUArchList()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoB.td271 let Predicates = [HasStdExtZbm, IsRV64] in
291 let Predicates = [HasStdExtZbr, IsRV64] in
304 let Predicates = [HasStdExtZbr, IsRV64] in
336 let Predicates = [HasStdExtZbm, IsRV64] in {
339 } // Predicates = [HasStdExtZbm, IsRV64]
352 let Predicates = [HasStdExtZbb, IsRV64] in {
359 } // Predicates = [HasStdExtZbb, IsRV64]
361 let Predicates = [HasStdExtZbb, IsRV64] in {
364 } // Predicates = [HasStdExtZbb, IsRV64]
366 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
[all …]
DRISCVInstrInfoC.td324 let Predicates = [HasStdExtC, IsRV64] in
358 let Predicates = [HasStdExtC, IsRV64] in
399 Predicates = [HasStdExtC, IsRV64] in
461 let Predicates = [HasStdExtC, IsRV64] in {
509 let Predicates = [HasStdExtC, IsRV64] in
569 let Predicates = [HasStdExtC, IsRV64] in
707 let Predicates = [HasStdExtC, IsRV64] in
718 let Predicates = [HasStdExtC, IsRV64] in
729 let Predicates = [HasStdExtC, IsRV64] in
740 let Predicates = [HasStdExtC, IsRV64] in
[all …]
DRISCVInstrInfoM.td45 let Predicates = [HasStdExtM, IsRV64] in {
56 } // Predicates = [HasStdExtM, IsRV64]
73 let Predicates = [HasStdExtM, IsRV64] in {
99 } // Predicates = [HasStdExtM, IsRV64]
DRISCVInstrInfoZfh.td184 let Predicates = [HasStdExtZfh, IsRV64] in {
208 } // Predicates = [HasStdExtZfh, IsRV64]
264 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
364 let Predicates = [HasStdExtZfh, IsRV64] in {
381 } // Predicates = [HasStdExtZfh, IsRV64]
DRISCVInstrInfoD.td170 let Predicates = [HasStdExtD, IsRV64] in {
204 } // Predicates = [HasStdExtD, IsRV64]
247 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
359 let Predicates = [HasStdExtD, IsRV64] in {
385 } // Predicates = [HasStdExtD, IsRV64]
DRISCVInstrInfoF.td206 let Predicates = [HasStdExtF, IsRV64] in {
230 } // Predicates = [HasStdExtF, IsRV64]
306 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
401 let Predicates = [HasStdExtF, IsRV64] in {
424 } // Predicates = [HasStdExtF, IsRV64]
DRISCVInstrInfo.td545 let Predicates = [IsRV64] in {
570 } // Predicates = [IsRV64]
646 let Predicates = [IsRV64] in {
650 } // Predicates = [IsRV64]
656 let Predicates = [IsRV64] in {
659 } // Predicates = [IsRV64]
781 let Predicates = [IsRV64] in {
797 } // Predicates = [IsRV64]
1128 let Predicates = [IsRV64, NotHasStdExtZbbOrZbp] in
1131 let Predicates = [IsRV64] in {
[all …]
DRISCVFrameLowering.cpp62 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue() local
67 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
110 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue() local
115 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
DRISCVInstrInfoA.td103 let Predicates = [HasStdExtA, IsRV64] in {
125 } // Predicates = [HasStdExtA, IsRV64]
317 let Predicates = [HasStdExtA, IsRV64] in {
391 } // Predicates = [HasStdExtA, IsRV64]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td320 let Predicates = [HasStdExtC, IsRV64] in
354 let Predicates = [HasStdExtC, IsRV64] in
395 Predicates = [HasStdExtC, IsRV64] in
457 let Predicates = [HasStdExtC, IsRV64] in {
505 let Predicates = [HasStdExtC, IsRV64] in
564 let Predicates = [HasStdExtC, IsRV64] in
702 let Predicates = [HasStdExtC, IsRV64] in
713 let Predicates = [HasStdExtC, IsRV64] in
724 let Predicates = [HasStdExtC, IsRV64] in
735 let Predicates = [HasStdExtC, IsRV64] in
[all …]
DRISCVInstrInfoM.td45 let Predicates = [HasStdExtM, IsRV64] in {
56 } // Predicates = [HasStdExtM, IsRV64]
73 let Predicates = [HasStdExtM, IsRV64] in {
97 } // Predicates = [HasStdExtM, IsRV64]
DRISCVInstrInfoD.td163 let Predicates = [HasStdExtD, IsRV64] in {
197 } // Predicates = [HasStdExtD, IsRV64]
240 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
344 let Predicates = [HasStdExtD, IsRV64] in {
365 } // Predicates = [HasStdExtD, IsRV64]
DRISCVInstrInfoF.td202 let Predicates = [HasStdExtF, IsRV64] in {
226 } // Predicates = [HasStdExtF, IsRV64]
300 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
397 let Predicates = [HasStdExtF, IsRV64] in {
419 } // Predicates = [HasStdExtF, IsRV64]
DRISCVInstrInfo.td495 let Predicates = [IsRV64] in {
520 } // Predicates = [IsRV64]
584 let Predicates = [IsRV64] in {
588 } // Predicates = [IsRV64]
594 let Predicates = [IsRV64] in {
597 } // Predicates = [IsRV64]
719 let Predicates = [IsRV64] in {
735 } // Predicates = [IsRV64]
1061 let Predicates = [IsRV64] in {
1098 } // Predicates = [IsRV64]
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp224 bool IsRV64; member
255 IsRV64 = o.IsRV64; in RISCVOperand()
618 bool isRV64() const { return IsRV64; } in isRV64()
659 bool IsRV64) { in createToken()
664 Op->IsRV64 = IsRV64; in createToken()
669 SMLoc E, bool IsRV64) { in createReg()
674 Op->IsRV64 = IsRV64; in createReg()
679 SMLoc E, bool IsRV64) { in createImm()
684 Op->IsRV64 = IsRV64; in createImm()
689 createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) { in createSysReg()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp260 bool IsRV64; member
299 IsRV64 = o.IsRV64; in RISCVOperand()
711 bool isRV64() const { return IsRV64; } in isRV64()
807 bool IsRV64) { in createToken()
812 Op->IsRV64 = IsRV64; in createToken()
817 SMLoc E, bool IsRV64) { in createReg()
822 Op->IsRV64 = IsRV64; in createReg()
827 SMLoc E, bool IsRV64) { in createImm()
832 Op->IsRV64 = IsRV64; in createImm()
837 createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) { in createSysReg()
[all …]
/external/llvm-project/clang/lib/Driver/ToolChains/
DRISCVToolchain.cpp152 bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64; in ConstructJob() local
154 if (IsRV64) { in ConstructJob()

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