| /external/llvm-project/clang/lib/Basic/Targets/ |
| D | ARM.cpp | 237 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), in ARMTargetInfo()
515 LDREX = 0; in handleTargetFeatures()
517 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; in handleTargetFeatures()
519 LDREX = LDREX_W; in handleTargetFeatures()
523 LDREX = LDREX_W | LDREX_H | LDREX_B; in handleTargetFeatures()
525 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; in handleTargetFeatures()
528 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; in handleTargetFeatures()
681 if (LDREX) in getTargetDefines()
682 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX)); in getTargetDefines()
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| D | ARM.h | 87 uint32_t LDREX; variable
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| /external/clang/lib/Basic/ |
| D | Targets.cpp | 4613 uint32_t LDREX; member in __anond4862fe70111::ARMTargetInfo
4833 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), in ARMTargetInfo()
5015 LDREX = 0; in handleTargetFeatures()
5017 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; in handleTargetFeatures()
5019 LDREX = LDREX_W; in handleTargetFeatures()
5023 LDREX = LDREX_W | LDREX_H | LDREX_B ; in handleTargetFeatures()
5025 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; in handleTargetFeatures()
5028 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; in handleTargetFeatures()
5143 if (LDREX) in getTargetDefines()
5144 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); in getTargetDefines()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 342 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
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| D | ARMExpandPseudoInsts.cpp | 1647 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 292 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX",
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| D | ARMScheduleSwift.td | 358 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
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| D | ARMExpandPseudoInsts.cpp | 1920 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
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| D | ARMScheduleA57.td | 141 "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY")>;
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| D | ARMInstrInfo.td | 5033 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5143 // FIXME Use InstAlias to generate LDREX/STREX pairs instead.
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 292 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX",
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| D | ARMScheduleSwift.td | 358 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
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| D | ARMScheduleA57.td | 129 "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY")>;
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| D | ARMExpandPseudoInsts.cpp | 2801 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
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| D | ARMInstrInfo.td | 5183 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5293 // FIXME Use InstAlias to generate LDREX/STREX pairs instead.
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| /external/llvm-project/llvm/docs/ |
| D | Atomics.rst | 449 which take some sort of exclusive lock on a cache line (``LDREX`` and ``STREX``
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| /external/llvm/docs/ |
| D | Atomics.rst | 447 which take some sort of exclusive lock on a cache line (``LDREX`` and ``STREX``
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| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x10.txt | 2227 Instruction 2097 S:0xC0042A2C 0xE8531F00 8 LDREX r1,[r3] false
2237 Instruction 2107 S:0xC0042A4E 0xE8531F00 10 LDREX r1,[r3] false
4406 Instruction 4204 S:0xC0043372 0xE8531F00 20 LDREX r1,[r3] false
4416 Instruction 4214 S:0xC0043394 0xE8531F00 10 LDREX r1,[r3] false
4556 Instruction 4351 S:0xC0046A30 0xE8541F00 19 LDREX r1,[r4] false
4567 Instruction 4362 S:0xC0046A30 0xE8541F00 18 LDREX r1,[r4] false
4593 Instruction 4386 S:0xC0046B02 0xE8510F00 5 LDREX r0,[r1] false
6629 Instruction 6327 S:0xC003C084 0xE8524F00 38 LDREX r4,[r2] false
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| D | etmv3_0x12.txt | 959 Instruction 934 S:0xC0043372 0xE8531F00 20 LDREX r1,[r3] false
969 Instruction 944 S:0xC0043394 0xE8531F00 10 LDREX r1,[r3] false
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| D | ptmv1_0x13.txt | 1528 Instruction 1456 S:0xC003C084 0xE8524F00 0 LDREX r4,[r2] false
6561 Instruction 6335 S:0xC0044596 0xE8531F00 0 LDREX r1,[r3] false
6571 Instruction 6345 S:0xC00445B8 0xE8531F00 0 LDREX r1,[r3] false
8071 Instruction 7790 S:0xC002EBF2 0xE8521F00 0 LDREX r1,[r2] false
8544 Instruction 8253 S:0xC003D636 0xE8551F00 0 LDREX r1,[r5] false
8754 Instruction 8457 S:0xC002EC46 0xE8521F00 0 LDREX r1,[r2] false
9442 Instruction 9137 S:0xC0042A2C 0xE8531F00 0 LDREX r1,[r3] false
9452 Instruction 9147 S:0xC0042A4E 0xE8531F00 0 LDREX r1,[r3] false
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 707 # LDREX/LDREXB/LDREXH/LDREXD
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| D | basic-arm-instructions.txt | 688 # LDREX/LDREXB/LDREXH/LDREXD
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| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 688 # LDREX/LDREXB/LDREXH/LDREXD
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| D | thumb2.txt | 707 # LDREX/LDREXB/LDREXH/LDREXD
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| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 184 19362U, // LDREX
2988 80U, // LDREX
7303 // LDA, LDAB, LDAEX, LDAEXB, LDAEXH, LDAH, LDRBT_POST, LDREX, LDREXB, LDR...
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