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/external/llvm/test/MC/Mips/micromips32r6/
D	invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 11 …addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate [all …]
/external/llvm-project/llvm/test/MC/Mips/micromips32r6/
D	invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 11 …addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate [all …]
/external/llvm/test/MC/Mips/micromips64r6/
D	invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 11 …addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran… 12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate [all …]
/external/llvm-project/llvm/test/MC/Mips/micromips/
D	invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 8 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 9 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 10 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 11 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 12 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 13 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate [all …]
/external/llvm-project/clang/test/FixIt/
D	fixit-availability.mm	10 // CHECK: fix-it:{{.}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, )) {\n " 11 // CHECK-NEXT: fix-it:{{.}}:{[[@LINE-2]]:14-[[@LINE-2]]:14}:"\n } else {\n // Fallback on ea… 13 // CHECK: fix-it:{{.}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, )) {\n " 14 // CHECK-NEXT: fix-it:{{.}}:{[[@LINE-2]]:29-[[@LINE-2]]:29}:"\n } else {\n // Fallback on ea… 16 // CHECK: fix-it:{{.}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, )) {\n " 17 // CHECK-NEXT: fix-it:{{.}}:{[[@LINE-2]]:19-[[@LINE-2]]:19}:"\n } else {\n // Fallback on ea… 20 // CHECK: fix-it:{{.}}:{[[@LINE-1]]:5-[[@LINE-1]]:5}:"if (@available(macOS 10.12, )) {\n " 21 // CHECK-NEXT: fix-it:{{.}}:{[[@LINE-2]]:20-[[@LINE-2]]:20}:"\n } else {\n // Fallback on ea… 24 // CHECK: fix-it:{{.}}:{[[@LINE-1]]:3-[[@LINE-1]]:3}:"if (@available(macOS 10.12, )) {\n " 25 // CHECK-NEXT: fix-it:{{.*}}:{[[@LINE-2]]:31-[[@LINE-2]]:31}:"\n } else {\n // Fallback on ea… [all …]
D	format-darwin.m	44 // CHECK: fix-it:"{{.}}":{[[@LINE-5]]:11-[[@LINE-5]]:13}:"%ld" 45 // CHECK: fix-it:"{{.}}":{[[@LINE-6]]:16-[[@LINE-6]]:16}:"(long)" 47 // CHECK: fix-it:"{{.}}":{[[@LINE-7]]:11-[[@LINE-7]]:13}:"%lu" 48 // CHECK: fix-it:"{{.}}":{[[@LINE-8]]:16-[[@LINE-8]]:16}:"(unsigned long)" 50 // CHECK: fix-it:"{{.}}":{[[@LINE-9]]:11-[[@LINE-9]]:13}:"%d" 51 // CHECK: fix-it:"{{.}}":{[[@LINE-10]]:16-[[@LINE-10]]:16}:"(int)" 53 // CHECK: fix-it:"{{.}}":{[[@LINE-11]]:11-[[@LINE-11]]:13}:"%u" 54 // CHECK: fix-it:"{{.}}":{[[@LINE-12]]:16-[[@LINE-12]]:16}:"(unsigned int)" 58 // CHECK: fix-it:"{{.}}":{[[@LINE-2]]:11-[[@LINE-2]]:13}:"%ld" 59 // CHECK: fix-it:"{{.}}":{[[@LINE-3]]:16-[[@LINE-3]]:16}:"(long)" [all …]
/external/llvm/test/MC/Mips/micromips/
D	invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 8 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 9 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 10 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 11 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 12 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 13 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate [all …]
/external/llvm-project/llvm/test/MC/Mips/msa/
D	invalid.s	8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate 17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate [all …]
D	invalid-64.s	8 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 9 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 10 insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate 11 insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate 12 insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 13 insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 14 insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate 15 insve.w $w0[4], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate 16 insve.d $w3[-1], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate 17 insve.d $w3[2], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate [all …]
/external/llvm/test/MC/Mips/msa/
D	invalid.s	8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate 17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate [all …]
D	invalid-64.s	8 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 9 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 10 insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate 11 insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate 12 insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 13 insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate 14 insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate 15 insve.w $w0[4], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate 16 insve.d $w3[-1], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate 17 insve.d $w3[2], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate [all …]
/external/llvm-project/llvm/test/MC/Mips/virt/
D	invalid.s	10 mfgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction 11 mfgc0 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 12 mfgc0 $4 # CHECK: :[[@LINE]]:3: error: too few operands for instruction 13 mfgc0 0, $4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 14 mfgc0 0, $4, $5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 15 mfgc0 $4, 0, $5 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 16 mfgc0 $4, $5, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 17 mfgc0 $4, $5, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 18 mfgc0 $4, $5, 0($4) # CHECK: :[[@LINE]]:18: error: invalid operand for instruction 19 mtgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction [all …]
/external/llvm/test/MC/Mips/
D	micromips-invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multip… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multip… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 8 addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 9 subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 10 andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 11 andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 12 and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 13 not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction [all …]
D	target-soft-float.s	12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 27 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 29 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 31 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled [all …]
/external/llvm-project/llvm/test/MC/Mips/
D	micromips-invalid.s	4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multip… 5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multip… 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 8 addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 9 subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 10 andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 11 andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 12 and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 13 not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction [all …]
D	target-soft-float.s	12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 27 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 29 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled 31 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled [all …]
/external/llvm-project/llvm/test/MC/Mips/crc/
D	invalid.s	9 crc32b $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match 10 crc32b $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match 11 crc32b $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction 12 crc32b $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction 13 crc32b 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 14 crc32b $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction 15 crc32b $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction 16 crc32b $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction 18 crc32h $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match 19 crc32h $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match [all …]
/external/llvm-project/llvm/test/MC/RISCV/
D	rva-aliases-invalid.s	8 lr.w a1, a0 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset 9 lr.w a1, foo # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset 10 lr.w a1, 1(a0) # CHECK: :[[@LINE]]:10: error: optional integer offset must be 0 11 lr.w a1, (foo) # CHECK: :[[@LINE]]:11: error: expected register 12 lr.w a1, 0(foo) # CHECK: :[[@LINE]]:12: error: expected register 13 lr.w a1, (f0) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 14 lr.w a1, 0(f0) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction 15 lr.w a1, 0(a0 # CHECK: :[[@LINE]]:17: error: expected ')' 16 lr.w a1, (a0 # CHECK: :[[@LINE]]:17: error: expected ')' 18 sc.w a2, a1, a0 # CHECK: :[[@LINE]]:14: error: expected '(' or optional integer offset [all …]
/external/llvm/test/MC/ARM/
D	v8_IT_manual.s	4 @ CHECK-NOT: [[@LINE+2]]:1: warning 8 @ CHECK-NOT: [[@LINE+2]]:1: warning 11 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block 14 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block 18 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block 22 @ CHECK-NOT: [[@LINE+2]]:1: warning 26 @ CHECK-NOT: [[@LINE+2]]:1: warning 30 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block 34 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block 38 @ CHECK-NOT: [[@LINE+2]]:1: warning [all …]
/external/llvm-project/llvm/test/MC/ARM/
D	v8_IT_manual.s	4 @ CHECK-NOT: :[[@LINE+2]]:1: warning 8 @ CHECK-NOT: :[[@LINE+2]]:1: warning 11 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block 14 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block 18 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block 22 @ CHECK-NOT: :[[@LINE+2]]:1: warning 26 @ CHECK-NOT: :[[@LINE+2]]:1: warning 30 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block 34 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block 38 @ CHECK-NOT: :[[@LINE+2]]:1: warning [all …]
D	mve-load-store.s	8 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 12 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 16 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 20 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 24 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 28 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 32 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 36 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 40 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction 44 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction [all …]
/external/llvm-project/llvm/test/MC/Mips/dsp/
D	invalid.s	4 extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate 5 extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate 6 extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 7 extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 10 extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate 11 extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate 12 extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 13 extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate [all …]
/external/llvm/test/MC/Mips/dsp/
D	invalid.s	4 extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate 5 extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate 6 extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 7 extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate 10 extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate 11 extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate 12 extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate 13 extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate [all …]
/external/llvm-project/llvm/test/MC/Mips/eva/
D	invalid_R6.s	9 …lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 10 …lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 11 …lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 12 …lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 13 …lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 14 …lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 15 …swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 16 …swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 17 …swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 18 …swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction [all …]
D	invalid-noeva-wrong-error.s	22 … cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction 23 … cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction 24 … cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction 25 …lbe $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 26 …lbe $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 27 …lbe $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 28 …lbue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 29 …lbue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 30 …lbue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… 31 …lhe $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct… [all …]

12 3 4 5 6 7 8 9 10 >>...49

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