| /external/rust/crates/gdbstub/src/arch/mips/reg/ |
| D | id.rs | 34 Lo2, enumerator
62 75 => MipsRegId::Lo2, in from_raw_id()
|
| /external/llvm-project/clang/test/SemaCXX/ |
| D | warn-bitfield-enum-conversion.cpp | 5 enum TwoBitsSigned { Lo2 = -2, Hi2 = 1 } two_bits_signed; enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 753 SDValue Lo2 = Node->getOperand(4); in trySelect() local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 753 SDValue Lo2 = Node->getOperand(4); in trySelect() local
755 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 343 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB() local
353 .add(Lo2); in selectG_ADD_SUB()
363 .add(Lo2) in selectG_ADD_SUB()
|
| D | SIISelLowering.cpp | 4021 SDValue Lo2, Hi2; in splitTernaryVectorOp() local
4022 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2); in splitTernaryVectorOp()
4026 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2, in splitTernaryVectorOp()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 353 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB() local
363 .add(Lo2); in selectG_ADD_SUB()
373 .add(Lo2) in selectG_ADD_SUB()
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| D | SIISelLowering.cpp | 4502 SDValue Lo2, Hi2; in splitTernaryVectorOp() local
4503 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2); in splitTernaryVectorOp()
4507 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2, in splitTernaryVectorOp()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 4980 dag Lo2 = (ORI (LIS 0x3333), 0x3333);
5002 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5045 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32));
5054 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333);
5063 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2),
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 5181 dag Lo2 = (ORI (LIS 0x3333), 0x3333);
5203 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5249 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32));
5258 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333);
5267 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2),
|