Searched refs:Lo4 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm-project/clang/test/SemaCXX/ |
| D | warn-bitfield-enum-conversion.cpp | 7 enum ThreeBitsSigned { Lo4 = -4, Hi4 = 3 } three_bits_signed; enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVAsmBackend.cpp | 209 unsigned Lo4 = (Value >> 1) & 0xf; in adjustFixupValue() local
214 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
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| /external/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVAsmBackend.cpp | 273 unsigned Lo4 = (Value >> 1) & 0xf; in adjustFixupValue() local
278 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 4982 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
5012 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),
5047 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32));
5056 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F);
5065 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4),
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 5183 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
5213 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),
5251 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32));
5260 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F);
5269 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4),
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