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Searched refs:MAP_WRITE (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/gallium/drivers/iris/
Diris_bufmgr.h296 #define MAP_WRITE PIPE_MAP_WRITE macro
304 #define MAP_FLAGS (MAP_READ | MAP_WRITE | MAP_ASYNC | \
Diris_border_color.c76 pool->map = iris_bo_map(NULL, pool->bo, MAP_WRITE); in iris_reset_border_color_pool()
Diris_bufmgr.c450 void *map = iris_bo_map(NULL, bo, MAP_WRITE | MAP_RAW); in alloc_bo_from_cache()
928 if (flags & MAP_WRITE) in print_flags()
1014 assert(bo->cache_coherent || !(flags & MAP_WRITE)); in iris_bo_map_cpu()
1184 if (!(flags & MAP_WRITE) && bo->bufmgr->has_llc) in can_map_cpu()
1204 return !(flags & MAP_WRITE); in can_map_cpu()
1780 buf->map = iris_bo_map(NULL, bo, MAP_WRITE | MAP_RAW); in gen_aux_map_buffer_alloc()
Diris_binder.c91 binder->map = iris_bo_map(NULL, binder->bo, MAP_WRITE); in binder_realloc()
Diris_screen.c733 bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE); in iris_init_identifier_bo()
Diris_batch.c360 batch->map = iris_bo_map(NULL, batch->bo, MAP_READ | MAP_WRITE); in create_batch()
Diris_resource.c748 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW); in iris_resource_init_aux_buf()
2084 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW); in iris_texture_subdata()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_buffer_objects.c261 void *map = brw_bo_map(brw, intel_obj->buffer, MAP_WRITE | MAP_ASYNC); in brw_buffer_subdata()
401 STATIC_ASSERT(GL_MAP_WRITE_BIT == MAP_WRITE); in brw_map_buffer_range()
444 if (access & MAP_WRITE) in brw_map_buffer_range()
Dintel_upload.c91 MAP_READ | MAP_WRITE | in brw_upload_space()
Dbrw_bufmgr.h276 #define MAP_WRITE GL_MAP_WRITE_BIT macro
Dbrw_program_cache.c216 void *map = brw_bo_map(brw, new_bo, MAP_READ | MAP_WRITE | in brw_cache_new_bo()
384 cache->map = brw_bo_map(brw, cache->bo, MAP_READ | MAP_WRITE | in brw_init_caches()
Dbrw_pipe_control.c382 bo_map = brw_bo_map(NULL, brw->workaround_bo, MAP_READ | MAP_WRITE); in init_identifier_bo()
Dbrw_bufmgr.c606 void *map = brw_bo_map(NULL, bo, MAP_WRITE | MAP_RAW); in bo_alloc_internal()
993 if (flags & MAP_WRITE) in print_flags()
1076 assert(bo->cache_coherent || !(flags & MAP_WRITE)); in brw_bo_map_cpu()
1237 if (!(flags & MAP_WRITE) && bo->bufmgr->has_llc) in can_map_cpu()
1254 return !(flags & MAP_WRITE); in can_map_cpu()
Dintel_batchbuffer.c246 grow->map = brw_bo_map(brw, grow->bo, MAP_READ | MAP_WRITE); in recreate_growing_buffer()
436 grow->map = brw_bo_map(brw, new_bo, MAP_READ | MAP_WRITE); in grow_buffer()
764 void *bo_map = brw_bo_map(brw, batch->batch.bo, MAP_WRITE); in submit_batch()
767 bo_map = brw_bo_map(brw, batch->state.bo, MAP_WRITE); in submit_batch()
Dbrw_program.c740 void *bo_map = brw_bo_map(brw, brw->shader_time.bo, MAP_READ | MAP_WRITE); in brw_collect_shader_time()
Dintel_tex_image.c269 void *map = brw_bo_map(brw, bo, MAP_WRITE | MAP_RAW); in intel_texsubimage_tiled_memcpy()
Dintel_screen.c2052 map = brw_bo_map(NULL, bo, MAP_WRITE); in intel_detect_pipelined_register()
Dintel_mipmap_tree.c1497 void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW); in intel_alloc_aux_buffer()
/external/mesa3d/src/intel/perf/
Dgen_perf_query.c48 #define MAP_WRITE (1 << 1) macro
796 void *map = perf_cfg->vtbl.bo_map(perf_ctx->ctx, query->oa.bo, MAP_WRITE); in gen_perf_begin_query()