| /external/lua/src/ |
| D | lopcodes.h | 105 #define MASK1(n,p) ((~((~(Instruction)0)<<(n)))<<(p)) macro
108 #define MASK0(n,p) (~MASK1(n,p))
114 #define GET_OPCODE(i) (cast(OpCode, ((i)>>POS_OP) & MASK1(SIZE_OP,0)))
116 ((cast(Instruction, o)<<POS_OP)&MASK1(SIZE_OP,POS_OP))))
121 #define getarg(i,pos,size) (cast_int(((i)>>(pos)) & MASK1(size,0)))
123 ((cast(Instruction, v)<<pos)&MASK1(size,pos))))
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | unal-altivec.ll | 35 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | unal-altivec.ll | 36 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
44 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | icmp-logical.ll | 6 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
7 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0
20 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
21 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
34 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
35 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7
48 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
49 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7
120 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15
121 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
|
| /external/llvm-project/mlir/test/Conversion/StandardToSPIRV/ |
| D | std-ops-to-spirv.mlir | 825 // CHECK: %[[MASK1:.+]] = spv.constant 255 : i32
826 // CHECK: %[[TMP1:.+]] = spv.ShiftLeftLogical %[[MASK1]], %[[OFFSET]] : i32, i32
828 // CHECK: %[[CLAMPED_VAL:.+]] = spv.BitwiseAnd %[[ARG1]], %[[MASK1]] : i32
851 // CHECK: %[[MASK1:.+]] = spv.constant 65535 : i32
852 // CHECK: %[[TMP1:.+]] = spv.ShiftLeftLogical %[[MASK1]], %[[OFFSET]] : i32, i32
854 // CHECK: %[[CLAMPED_VAL:.+]] = spv.BitwiseAnd %[[ARG2]], %[[MASK1]] : i32
933 // CHECK: %[[MASK1:.+]] = spv.constant 255 : i32
934 // CHECK: %[[TMP1:.+]] = spv.ShiftLeftLogical %[[MASK1]], %[[OFFSET]] : i32, i32
936 // CHECK: %[[CLAMPED_VAL:.+]] = spv.BitwiseAnd %[[ARG1]], %[[MASK1]] : i32
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | wave32.ll | 237 ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
238 ; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec
241 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
242 ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
244 ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
245 ; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]]
253 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], exec_lo
254 ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], exec
|
| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 382 return MASK1;
439 return_token_or_DOT(require_ARB_fp, MASK1);
450 return MASK1;
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| D | program_parse.y | 196 %token <swiz_mask> MASK4 MASK3 MASK2 MASK1 SWIZZLE
937 addrComponent: MASK1
948 addrWriteMask: MASK1
960 scalarSuffix: MASK1;
962 swizzleSuffix: MASK1
968 optionalMask: MASK4 | MASK3 | MASK2 | MASK1
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| /external/llvm-project/llvm/test/Instrumentation/HeapProfiler/ |
| D | masked-load-store.ll | 85 ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
86 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
199 ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
200 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
|
| /external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/ |
| D | asan-masked-load-store.ll | 93 ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
94 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
221 ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
222 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/X86/ |
| D | x86-masked-memops.ll | 104 ; CHECK-NEXT: [[MASK1:%.*]] = and <8 x i1> [[ICMP0]], [[ICMP1]]
106 …lvm.masked.load.v8f32.p0v8f32(<8 x float>* [[CASTVEC]], i32 1, <8 x i1> [[MASK1]], <8 x float> zer…
350 ; CHECK-NEXT: [[MASK1:%.*]] = and <4 x i1> [[ICMP0]], [[ICMP1]]
352 ….masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[CASTVEC]], i32 1, <4 x i1> [[MASK1]])
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | uniform-cfg.ll | 310 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
340 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/ |
| D | core_cm3.h | 853 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_sc300.h | 835 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_cm4.h | 914 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_cm7.h | 1116 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/ |
| D | core_cm3.h | 853 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_sc300.h | 835 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_cm4.h | 914 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|
| D | core_cm7.h | 1116 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ member
|