| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 517 MFENCE, enumerator
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| D | X86InstrInfo.td | 127 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| D | X86InstrSSE.td | 3688 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3693 def : Pat<(X86MFence), (MFENCE)>;
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 386 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1318 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
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| D | X86LoadValueInjectionLoadHardening.cpp | 771 if (!MI.mayLoadOrStore() || MI.getOpcode() == X86::MFENCE || in instrUsesRegToAccessMemory()
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| D | X86ISelLowering.h | 646 MFENCE, enumerator
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| D | X86SchedBroadwell.td | 702 MFENCE,
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| D | X86SchedHaswell.td | 1104 MFENCE,
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| D | X86SchedSkylakeClient.td | 824 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
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| D | X86SchedSkylakeServer.td | 893 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
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| D | X86InstrSSE.td | 3199 def MFENCE : I<0xAE, MRM6X, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3203 def : Pat<(X86MFence), (MFENCE)>;
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| D | X86InstrInfo.td | 137 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 385 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1693 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
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| D | X86ISelLowering.h | 542 MFENCE, enumerator
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| D | X86SchedBroadwell.td | 699 MFENCE,
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| D | X86SchedSkylakeClient.td | 821 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
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| D | X86SchedHaswell.td | 1101 MFENCE,
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| D | X86SchedSkylakeServer.td | 882 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
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| D | X86InstrInfo.td | 135 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| D | X86InstrSSE.td | 3194 def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3198 def : Pat<(X86MFence), (MFENCE)>;
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| /external/llvm-project/llvm/docs/ |
| D | Atomics.rst | 438 fences generate an ``MFENCE``, other fences do not cause any code to be
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| /external/llvm/docs/ |
| D | Atomics.rst | 436 fences generate an ``MFENCE``, other fences do not cause any code to be
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 6530 {DBGFIELD("MFENCE") 1, false, false, 6, 2, 1, 1, 0, 0}, // #841
7907 {DBGFIELD("MFENCE") 1, false, false, 248, 2, 1, 1, 0, 0}, // #841
9284 {DBGFIELD("MFENCE") 2, false, false, 801, 2, 3, 1, 0, 0}, // #841
10661 {DBGFIELD("MFENCE") 1, false, false, 135, 2, 1, 1, 0, 0}, // #841
12038 {DBGFIELD("MFENCE") 3, false, false, 792, 3, 22, 1, 0, 0}, // #841
13415 {DBGFIELD("MFENCE") 1, false, false, 3711, 3, 1, 1, 0, 0}, // #841
14792 {DBGFIELD("MFENCE") 2, false, false, 801, 2, 3, 1, 0, 0}, // #841
16169 {DBGFIELD("MFENCE") 1, false, false, 129, 1, 1, 1, 0, 0}, // #841
17546 {DBGFIELD("MFENCE") 3, false, false, 792, 3, 22, 1, 0, 0}, // #841
18923 {DBGFIELD("MFENCE") 1, false, false, 2, 1, 1, 1, 0, 0}, // #841
[all …]
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| /external/mesa3d/docs/relnotes/ |
| D | 19.1.0.rst | 2281 - intel/fs,vec4: Use g0 as the header for MFENCE
2282 - intel/fs: Do a stalling MFENCE in endInvocationInterlock()
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1.inc | 1401 10294U, // MFENCE
10258 0U, // MFENCE
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