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Searched refs:MI2 (Results 1 – 25 of 46) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp197 MachineInstr *MI2 = nullptr,
398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
475 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
485 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
[all …]
/external/llvm-project/llvm/unittests/CodeGen/
DMachineInstrTest.cpp65 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
66 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
67 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
71 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); in TEST()
72 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); in TEST()
74 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); in TEST()
75 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); in TEST()
99 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
100 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); in checkHashAndIsEqualMatch()
101 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); in checkHashAndIsEqualMatch()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFMIPeephole.cpp413 MachineInstr *MI2 = nullptr; in eliminateTruncSeq() local
429 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
432 if (!MI2 || in eliminateTruncSeq()
433 MI2->getOpcode() != BPF::SLL_ri || in eliminateTruncSeq()
434 MI2->getOperand(2).getImm() != 32) in eliminateTruncSeq()
438 SrcReg = MI2->getOperand(1).getReg(); in eliminateTruncSeq()
489 if (MI2) in eliminateTruncSeq()
490 MI2->eraseFromParent(); in eliminateTruncSeq()
/external/llvm-project/llvm/lib/Target/BPF/
DBPFMIPeephole.cpp462 MachineInstr *MI2 = nullptr; in eliminateTruncSeq() local
478 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
481 if (!MI2 || in eliminateTruncSeq()
482 MI2->getOpcode() != BPF::SLL_ri || in eliminateTruncSeq()
483 MI2->getOperand(2).getImm() != 32) in eliminateTruncSeq()
487 SrcReg = MI2->getOperand(1).getReg(); in eliminateTruncSeq()
538 if (MI2) in eliminateTruncSeq()
539 MI2->eraseFromParent(); in eliminateTruncSeq()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp460 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
495 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
496 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
499 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
500 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
505 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
506 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
517 MI2->getParent()); in hoistAndMergeSGPRInits()
524 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
529 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
DAMDGPUSubtarget.cpp769 MachineInstr &MI2 = *SU.getInstr(); in apply() local
770 if (!MI2.mayLoad() && !MI2.mayStore()) { in apply()
780 if ((TII->isVMEM(MI1) && TII->isVMEM(MI2)) || in apply()
781 (TII->isFLAT(MI1) && TII->isFLAT(MI2)) || in apply()
782 (TII->isSMRD(MI1) && TII->isSMRD(MI2)) || in apply()
783 (TII->isDS(MI1) && TII->isDS(MI2))) { in apply()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp454 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
489 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
490 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
493 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
494 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
499 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
500 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
511 MI2->getParent()); in hoistAndMergeSGPRInits()
518 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
523 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDFAPacketizer.cpp302 const MachineInstr &MI2, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
DTargetInstrInfo.cpp677 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
681 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
684 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
692 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
697 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
699 std::swap(MI1, MI2); in hasReassociableSibling()
/external/llvm-project/llvm/lib/CodeGen/
DDFAPacketizer.cpp302 const MachineInstr &MI2, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
DTargetInstrInfo.cpp712 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
716 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
719 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
727 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
732 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
734 std::swap(MI1, MI2); in hasReassociableSibling()
/external/python/pybind11/tests/
Dtest_multiple_inheritance.py69 class MI2(B1, m.Base1, m.Base2): class
75 class MI3(MI2):
77 MI2.__init__(self, i, j)
127 mi2 = MI2(3, 4)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp155 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
156 if (!QII->isHVXVec(MI2)) in apply()
158 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp571 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
575 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
586 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
593 std::swap(MI1, MI2); in hasReassociableSibling()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp225 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
226 if (!QII->isHVXVec(MI2)) in apply()
228 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp250 const MachineInstr &MI2, unsigned N2) const;
365 const MachineInstr &MI2, in getAddrDispShift() argument
368 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
/external/clang/test/Analysis/
Dpadding_cpp.cpp102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
/external/llvm-project/clang/test/Analysis/
Dpadding_cpp.cpp102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
/external/llvm-project/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp278 const MachineInstr &MI2, unsigned N2) const;
401 const MachineInstr &MI2, in getAddrDispShift() argument
404 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp278 const MachineInstr &MI2, unsigned N2) const;
401 const MachineInstr &MI2, in getAddrDispShift() argument
404 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DDFAPacketizer.h190 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
/external/llvm-project/llvm/include/llvm/CodeGen/
DDFAPacketizer.h190 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.h97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp317 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
321 dbgs() << " " << MI2; in ExpandFPMLxInstruction()

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