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Searched refs:MSKOR (Results 1 – 17 of 17) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstore-global.ll8 ; EG: MEM_RAT MSKOR
9 ; EG-NOT: MEM_RAT MSKOR
11 ; CM: MEM_RAT MSKOR
12 ; CM-NOT: MEM_RAT MSKOR
24 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
25 ; EG-NOT: MEM_RAT MSKOR
44 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
45 ; EG-NOT: MEM_RAT MSKOR
71 ; EG: MEM_RAT MSKOR
72 ; EG: MEM_RAT MSKOR
[all …]
Dcttz_zero_undef.ll86 ; EG: MEM_RAT MSKOR
98 ; EG: MEM_RAT MSKOR
135 ; EG: MEM_RAT MSKOR
148 ; EG: MEM_RAT MSKOR
250 ; EG: MEM_RAT MSKOR
265 ; EG: MEM_RAT MSKOR
Dsext-in-reg-failure-r600.ll4 ; EG: MEM_{{.*}} MSKOR [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
Dfp32_to_fp16.ll12 ; EG: MEM_RAT MSKOR
Dr600.bitcast.ll148 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T6.X
Dctlz.ll346 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1005 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1078 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
1149 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
Dshl.ll132 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
188 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
246 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
315 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
374 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
Dload-global-i16.ll63 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
89 ; CM-NEXT: MEM_RAT MSKOR T0.XW, T1.X
261 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
296 ; CM-NEXT: MEM_RAT MSKOR T5.XW, T8.X
Dload-constant-i16.ll60 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
202 ; EG-NEXT: MEM_RAT MSKOR T5.XW, T8.X
/external/llvm/test/CodeGen/AMDGPU/
Dstore.ll10 ; EG: MEM_RAT MSKOR
20 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
50 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
101 ; EG: MEM_RAT MSKOR
102 ; EG-NOT: MEM_RAT MSKOR
194 ; EG: MEM_RAT MSKOR
204 ; EG: MEM_RAT MSKOR
/external/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_instruction_gds.h123 MSKOR, enumerator
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td180 // MSKOR instructions are atomic memory instructions used mainly for storing
183 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
DEvergreenInstructions.td54 "MSKOR $rw_gpr.XW, $index_gpr",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td262 // MSKOR instructions are atomic memory instructions used mainly for storing
265 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
DEvergreenInstructions.td60 "MSKOR $rw_gpr.XW, $index_gpr",
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td246 // MSKOR instructions are atomic memory instructions used mainly for storing
249 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
DEvergreenInstructions.td69 "MSKOR $rw_gpr.XW, $index_gpr",