| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 42 MTBUF = 9 variable in Format
77 elif self == Format.MTBUF:
1334 MTBUF = { variable
1352 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MTBUF:
1353 opcode(name, gfx7, gfx9, gfx10, Format.MTBUF)
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| D | aco_opt_value_numbering.cpp | 109 case Format::MTBUF: in operator ()()
254 case Format::MTBUF: { in operator ()()
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| D | aco_ir.cpp | 146 case Format::MTBUF: in get_sync_info()
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| D | aco_validate.cpp | 215 … ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1); in validate_ir()
428 case Format::MTBUF: in validate_ir()
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| D | aco_ir.h | 82 MTBUF = 9, enumerator
937 return format == Format::MTBUF || in isVMEM()
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| D | aco_print_ir.cpp | 520 case Format::MTBUF: { in print_instr_format_specific()
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| D | aco_insert_NOPs.cpp | 494 bool consider_buf = (instr->format == Format::MUBUF || instr->format == Format::MTBUF) && in handle_instruction_gfx6()
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| D | aco_insert_waitcnt.cpp | 815 case Format::MTBUF: in gen()
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| D | aco_assembler.cpp | 392 case Format::MTBUF: { in emit_instruction()
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| D | aco_insert_exec_mask.cpp | 139 } else if (instr->format == Format::MTBUF) { in needs_exact()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIPostRABundler.cpp | 93 const uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF | in runOnMachineFunction()
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| D | SIInstrFormats.td | 40 field bit MTBUF = 0;
160 let TSFlags{18} = MTBUF;
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| D | SIDefines.h | 47 MTBUF = 1 << 18, enumerator
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| D | SIInstrInfo.h | 460 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
464 return get(Opcode).TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
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| D | BUFInstructions.td | 54 // MTBUF classes
86 let MTBUF = 1;
1112 // MTBUF Instructions
1710 // MTBUF Patterns
2133 // MTBUF - GFX10.
2166 // MTBUF - GFX6, GFX7, GFX10.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 39 field bits<1> MTBUF = 0;
75 let TSFlags{17} = MTBUF;
700 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
705 let MTBUF = 1;
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| D | SIDefines.h | 36 MTBUF = 1 << 17, enumerator
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| D | SIInstrInfo.h | 288 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
292 return get(Opcode).TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
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| D | SIInstrInfo.td | 2814 // MTBUF classes
2818 MTBUF <outs, ins, "", pattern>,
2826 MTBUF <outs, ins, asm, []>,
2834 MTBUF <outs, ins, asm, []>,
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| D | SIInstructions.td | 1092 // MTBUF Instructions
3296 // MTBUF Patterns
3300 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 39 field bit MTBUF = 0;
151 let TSFlags{17} = MTBUF;
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| D | SIDefines.h | 46 MTBUF = 1 << 17, enumerator
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| D | SIInstrInfo.h | 454 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
458 return get(Opcode).TSFlags & SIInstrFlags::MTBUF; in isMTBUF()
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| D | BUFInstructions.td | 54 // MTBUF classes
86 let MTBUF = 1;
1101 // MTBUF Instructions
1683 // MTBUF Patterns
2091 // MTBUF - GFX10.
2124 // MTBUF - GFX6, GFX7, GFX10.
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| /external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 710 if (Desc.TSFlags & SIInstrFlags::MTBUF) { in printOperand()
|