Searched refs:MVEBU_DRAM_PWR_CTRL_REG (Results 1 – 1 of 1) sorted by relevance
168 #define MVEBU_DRAM_PWR_CTRL_REG (MVEBU_DRAM_REG_BASE + 0x54) macro405 mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | in a3700_en_ddr_self_refresh()