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Searched refs:MVEBU_PM_NB_PWR_CTRL_REG (Results 1 – 1 of 1) sorted by relevance

/external/arm-trusted-firmware/plat/marvell/armada/a3k/common/
Dplat_pm.c76 #define MVEBU_PM_NB_PWR_CTRL_REG (MVEBU_PMSU_REG_BASE) macro
346 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); in a3700_set_gen_pwr_off_option()
376 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_PWR_DN_CNT_SEL); in a3700_en_ddr_self_refresh()
438 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_SB_PWR_DWN); in a3700_pwr_dn_sb()