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Searched refs:Mask0 (Results 1 – 18 of 18) sorted by relevance

/external/oboe/samples/RhythmGame/third_party/glm/simd/
Dinteger.h14 glm_uvec4 const Mask0 = _mm_set1_epi32(0x55555555); in glm_i128_interleave() local
52 Reg1 = _mm_and_si128(Reg1, Mask0); in glm_i128_interleave()
68 glm_uvec4 const Mask0 = _mm_set1_epi32(0x55555555); in glm_i128_interleave2() local
105 Reg1 = _mm_and_si128(Reg1, Mask0); in glm_i128_interleave2()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZTDC.cpp289 int Mask0, Mask1; in convertLogicOp() local
291 std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))]; in convertLogicOp()
298 Mask = Mask0 & Mask1; in convertLogicOp()
301 Mask = Mask0 | Mask1; in convertLogicOp()
304 Mask = Mask0 ^ Mask1; in convertLogicOp()
/external/llvm/lib/Target/SystemZ/
DSystemZTDC.cpp289 int Mask0, Mask1; in convertLogicOp() local
291 std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))]; in convertLogicOp()
298 Mask = Mask0 & Mask1; in convertLogicOp()
301 Mask = Mask0 | Mask1; in convertLogicOp()
304 Mask = Mask0 ^ Mask1; in convertLogicOp()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZTDC.cpp297 int Mask0, Mask1; in convertLogicOp() local
299 std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))]; in convertLogicOp()
306 Mask = Mask0 & Mask1; in convertLogicOp()
309 Mask = Mask0 | Mask1; in convertLogicOp()
312 Mask = Mask0 ^ Mask1; in convertLogicOp()
/external/llvm-project/llvm/test/tools/llvm-readobj/ELF/
Dmips-options-sec.test12 # CHECK-NEXT: Co-Proc Mask0: 0x88776655
20 # CHECK-NEXT: Co-Proc Mask0: 0x0
40 # NAME-ERR-FOUND-NEXT: Co-Proc Mask0: 0x88776655
48 # NAME-ERR-FOUND-NEXT: Co-Proc Mask0: 0x0
133 # KIND-NEXT: Co-Proc Mask0: 0x0
Dmips-reginfo.test10 # OPTIONS-NEXT: Co-Proc Mask0: 0x88776655
/external/llvm/test/tools/llvm-readobj/
Dmips-reginfo.test6 CHECK-NEXT: Co-Proc Mask0: 0x0
Dmips-options-sec.test7 CHECK-NEXT: Co-Proc Mask0: 0x0
/external/llvm-project/lld/test/ELF/
Dmips-reginfo.s21 # CHECK-NEXT: Co-Proc Mask0: 0x0
Dmips-options.s38 # CHECK-NEXT: Co-Proc Mask0: 0x0
/external/llvm-project/llvm/lib/Transforms/Scalar/
DEarlyCSE.cpp841 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
843 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
845 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
847 auto *Vec0 = dyn_cast<ConstantVector>(Mask0); in isNonTargetIntrinsicMatch()
/external/llvm/test/CodeGen/X86/
Dmasked_gather_scatter.ll180 ; SCALAR: %Mask0 = extractelement <16 x i1> %imask, i32 0
181 ; SCALAR-NEXT: %ToStore0 = icmp eq i1 %Mask0, true
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp6032 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1)); in matchBSwapHWordOrAndAnd() local
6034 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
6036 if (Mask0->getAPIntValue() != 0xff00ff00 || in matchBSwapHWordOrAndAnd()
20051 SmallVector<int, 16> Mask0(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
20058 Mask0[i] = M; in foldShuffleOfConcatUndefs()
20067 if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || in foldShuffleOfConcatUndefs()
20075 SDValue Shuf0 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask0); in foldShuffleOfConcatUndefs()
20549 ArrayRef<int> Mask0 = Shuf0->getMask(); in simplifyShuffleOfShuffle() local
20558 if (Mask0[Mask[i]] != Mask0[i]) in simplifyShuffleOfShuffle()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp3869 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); in lowerU64ToF32BitOps() local
3872 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); in lowerU64ToF32BitOps()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp18681 SmallVector<int, 16> Mask0(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
18688 Mask0[i] = M; in foldShuffleOfConcatUndefs()
18697 if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || in foldShuffleOfConcatUndefs()
18705 SDValue Shuf0 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask0); in foldShuffleOfConcatUndefs()
19129 ArrayRef<int> Mask0 = Shuf0->getMask(); in simplifyShuffleOfShuffle() local
19138 if (Mask0[Mask[i]] != Mask0[i]) in simplifyShuffleOfShuffle()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp5026 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); in lowerU64ToF32BitOps() local
5029 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); in lowerU64ToF32BitOps()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp5933 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems); in insert1BitVector() local
5934 Mask0.flipAllBits(); in insert1BitVector()
5935 SDValue CMask0 = DAG.getConstant(Mask0, dl, MVT::getIntegerVT(NumElems)); in insert1BitVector()
7224 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
7225 scaleShuffleMask<int>(MaskSize / SrcMask0.size(), SrcMask0, Mask0); in getFauxShuffleMask()
7228 if (Mask0[i] == SM_SentinelUndef && Mask1[i] == SM_SentinelUndef) in getFauxShuffleMask()
7230 else if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
7233 Mask.push_back(Mask0[i]); in getFauxShuffleMask()
7234 else if (Mask0[i] == SM_SentinelZero) in getFauxShuffleMask()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp6192 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems); in insert1BitVector() local
6193 Mask0.flipAllBits(); in insert1BitVector()
6194 SDValue CMask0 = DAG.getConstant(Mask0, dl, MVT::getIntegerVT(NumElems)); in insert1BitVector()
7482 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
7483 narrowShuffleMaskElts(MaskSize / SrcMask0.size(), SrcMask0, Mask0); in getFauxShuffleMask()
7486 if (Mask0[i] == SM_SentinelUndef && Mask1[i] == SM_SentinelUndef) in getFauxShuffleMask()
7488 else if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
7492 else if (Mask0[i] == SM_SentinelZero) in getFauxShuffleMask()