Searched refs:NUM_BANKS (Results 1 – 8 of 8) sorted by relevance
54 unsigned int NUM_BANKS : 3; member74 unsigned int NUM_BANKS : 3;
48 uint16_t free_slot_idx[NUM_BANKS]; /* Up to 1KiB. Move to dynamic? */126 sizeof(uint8_t) * 65536 + sizeof(FN(Bank)) * NUM_BANKS; in FN()138 const size_t bank = key & (NUM_BANKS - 1); in FN()243 const size_t bank = key & (NUM_BANKS - 1); in FN()
288 #define NUM_BANKS 1 macro300 #undef NUM_BANKS304 #define NUM_BANKS 512 macro310 #undef NUM_BANKS
60 #define NUM_BANKS (NUM_VGPR_BANKS + NUM_SGPR_BANKS) macro255 for (unsigned L = 0; L < NUM_BANKS; ++L) in dumpFreeBanks()645 for (int Bank = 0; Bank < NUM_BANKS; ++Bank) { in tryReassign()
61 #define NUM_BANKS (NUM_VGPR_BANKS + NUM_SGPR_BANKS) macro278 for (unsigned L = 0; L < NUM_BANKS; ++L) in dumpFreeBanks()712 for (int Bank = 0; Bank < NUM_BANKS; ++Bank) { in tryReassign()
806 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1); in radv_amdgpu_winsys_bo_set_metadata()851 md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in radv_amdgpu_winsys_bo_get_metadata()
2242 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in ac_surface_set_bo_metadata()2297 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1); in ac_surface_get_bo_metadata()
1110 switch (gbAddrConfig.bits.NUM_BANKS) in HwlInitGlobalParams()