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Searched refs:NUM_VGPR_BANKS (Results 1 – 2 of 2) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNRegBankReassign.cpp58 #define NUM_VGPR_BANKS 4 macro
60 #define NUM_BANKS (NUM_VGPR_BANKS + NUM_SGPR_BANKS)
61 #define SGPR_BANK_OFFSET NUM_VGPR_BANKS
288 return Reg % NUM_VGPR_BANKS; in getPhysRegBank()
324 Mask <<= (Bank == -1) ? Reg % NUM_VGPR_BANKS : unsigned(Bank); in getRegBankMask()
325 return (Mask | (Mask >> NUM_VGPR_BANKS)) & VGPR_BANK_MASK; in getRegBankMask()
376 if (!(LM & 1) && (Bank < NUM_VGPR_BANKS)) { in analyzeInst()
378 if (countPopulation(LM) >= NUM_VGPR_BANKS) in analyzeInst()
380 ShiftedBank = (Bank + countTrailingZeros(LM)) % NUM_VGPR_BANKS; in analyzeInst()
462 if ((Mask & VGPR_BANK_MASK) && (Size < NUM_VGPR_BANKS)) { in getFreeBanks()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNRegBankReassign.cpp59 #define NUM_VGPR_BANKS 4 macro
61 #define NUM_BANKS (NUM_VGPR_BANKS + NUM_SGPR_BANKS)
62 #define SGPR_BANK_OFFSET NUM_VGPR_BANKS
322 return RegNo % NUM_VGPR_BANKS; in getPhysRegBank()
365 Mask <<= (Bank == -1) ? RegNo % NUM_VGPR_BANKS : uint32_t(Bank); in getRegBankMask()
366 return (Mask | (Mask >> NUM_VGPR_BANKS)) & VGPR_BANK_MASK; in getRegBankMask()
419 if (TRI->getNumCoveredRegs(LM) >= NUM_VGPR_BANKS) in analyzeInst()
434 if (Bank < NUM_VGPR_BANKS) { in analyzeInst()
435 unsigned Shift = ((NUM_VGPR_BANKS + Offset) - RegOffset); in analyzeInst()
436 ShiftedBank = (Bank + Shift) % NUM_VGPR_BANKS; in analyzeInst()
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