1 #ifndef NVE4_COMPUTE_XML 2 #define NVE4_COMPUTE_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/envytools/envytools/ 8 git clone https://github.com/envytools/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - rnndb/graph/gk104_compute.xml ( 10182 bytes, from 2014-09-25 06:32:11) 12 - rnndb/copyright.xml ( 6456 bytes, from 2014-12-31 02:13:31) 13 - rnndb/nvchipsets.xml ( 2759 bytes, from 2014-10-05 01:51:02) 14 - rnndb/fifo/nv_object.xml ( 15326 bytes, from 2014-09-25 06:32:11) 15 - rnndb/g80_defs.xml ( 18175 bytes, from 2014-09-25 06:32:11) 16 - rnndb/graph/gk104_p2mf.xml ( 2376 bytes, from 2014-09-25 06:32:11) 17 18 Copyright (C) 2006-2014 by the following authors: 19 - Artur Huillet <arthur.huillet@free.fr> (ahuillet) 20 - Ben Skeggs (darktama, darktama_) 21 - B. R. <koala_br@users.sourceforge.net> (koala_br) 22 - Carlos Martin <carlosmn@users.sf.net> (carlosmn) 23 - Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr) 24 - Dawid Gajownik <gajownik@users.sf.net> (gajownik) 25 - Dmitry Baryshkov 26 - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag) 27 - EdB <edb_@users.sf.net> (edb_) 28 - Erik Waling <erikwailing@users.sf.net> (erikwaling) 29 - Francisco Jerez <currojerez@riseup.net> (curro) 30 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 31 - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome) 32 - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy) 33 - Laurent Carlier <lordheavym@gmail.com> (lordheavy) 34 - Luca Barbieri <luca@luca-barbieri.com> (lb, lb1) 35 - Maarten Maathuis <madman2003@gmail.com> (stillunknown) 36 - Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin) 37 - Mark Carey <mark.carey@gmail.com> (careym) 38 - Matthieu Castet <matthieu.castet@parrot.com> (mat-c) 39 - nvidiaman <nvidiaman@users.sf.net> (nvidiaman) 40 - Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata) 41 - Pekka Paalanen <pq@iki.fi> (pq, ppaalanen) 42 - Peter Popov <ironpeter@users.sf.net> (ironpeter) 43 - Richard Hughes <hughsient@users.sf.net> (hughsient) 44 - Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar) 45 - Serge Martin 46 - Simon Raffeiner 47 - Stephane Loeuillet <leroutier@users.sf.net> (leroutier) 48 - Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu) 49 - sturmflut <sturmflut@users.sf.net> (sturmflut) 50 - Sylvain Munaut <tnt@246tNt.com> 51 - Victor Stinner <victor.stinner@haypocalc.com> (haypo) 52 - Wladmir van der Laan <laanwj@gmail.com> (miathan6) 53 - Younes Manton <younes.m@gmail.com> (ymanton) 54 55 Permission is hereby granted, free of charge, to any person obtaining 56 a copy of this software and associated documentation files (the 57 "Software"), to deal in the Software without restriction, including 58 without limitation the rights to use, copy, modify, merge, publish, 59 distribute, sublicense, and/or sell copies of the Software, and to 60 permit persons to whom the Software is furnished to do so, subject to 61 the following conditions: 62 63 The above copyright notice and this permission notice (including the 64 next paragraph) shall be included in all copies or substantial 65 portions of the Software. 66 67 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 68 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 69 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 70 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 71 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 72 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 73 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 74 */ 75 76 77 78 79 #define NVE4_COMPUTE_UNK0144 0x00000144 80 81 #define NVE4_COMPUTE_UPLOAD 0x00000000 82 83 #define NVE4_COMPUTE_UPLOAD_LINE_LENGTH_IN 0x00000180 84 85 #define NVE4_COMPUTE_UPLOAD_LINE_COUNT 0x00000184 86 87 #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_HIGH 0x00000188 88 89 #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_LOW 0x0000018c 90 91 #define NVE4_COMPUTE_UPLOAD_DST_PITCH 0x00000190 92 93 #define NVE4_COMPUTE_UPLOAD_DST_TILE_MODE 0x00000194 94 95 #define NVE4_COMPUTE_UPLOAD_DST_WIDTH 0x00000198 96 97 #define NVE4_COMPUTE_UPLOAD_DST_HEIGHT 0x0000019c 98 99 #define NVE4_COMPUTE_UPLOAD_DST_DEPTH 0x000001a0 100 101 #define NVE4_COMPUTE_UPLOAD_DST_Z 0x000001a4 102 103 #define NVE4_COMPUTE_UPLOAD_DST_X 0x000001a8 104 105 #define NVE4_COMPUTE_UPLOAD_DST_Y 0x000001ac 106 107 #define NVE4_COMPUTE_UPLOAD_EXEC 0x000001b0 108 #define NVE4_COMPUTE_UPLOAD_EXEC_LINEAR 0x00000001 109 #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__MASK 0x0000007e 110 #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__SHIFT 1 111 #define NVE4_COMPUTE_UPLOAD_EXEC_BUF_NOTIFY 0x00000300 112 #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__MASK 0x0000f000 113 #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__SHIFT 12 114 115 #define NVE4_COMPUTE_UPLOAD_DATA 0x000001b4 116 117 #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_HIGH 0x000001dc 118 119 #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_LOW 0x000001e0 120 121 #define NVE4_COMPUTE_UPLOAD_QUERY_SEQUENCE 0x000001e4 122 123 #define NVE4_COMPUTE_UPLOAD_UNK01F0 0x000001f0 124 125 #define NVE4_COMPUTE_UPLOAD_UNK01F4 0x000001f4 126 127 #define NVE4_COMPUTE_UPLOAD_UNK01F8 0x000001f8 128 129 #define NVE4_COMPUTE_UPLOAD_UNK01FC 0x000001fc 130 131 #define NVE4_COMPUTE_SHARED_BASE 0x00000214 132 133 #define NVE4_COMPUTE_MEM_BARRIER 0x0000021c 134 #define NVE4_COMPUTE_MEM_BARRIER_UNK0__MASK 0x00000007 135 #define NVE4_COMPUTE_MEM_BARRIER_UNK0__SHIFT 0 136 #define NVE4_COMPUTE_MEM_BARRIER_UNK4 0x00000010 137 #define NVE4_COMPUTE_MEM_BARRIER_UNK12 0x00001000 138 139 #define NVE4_COMPUTE_UNK0240 0x00000240 140 141 #define NVE4_COMPUTE_UNK244_TIC_FLUSH 0x00000244 142 143 #define NVE4_COMPUTE_UNK0248 0x00000248 144 #define NVE4_COMPUTE_UNK0248_UNK0__MASK 0x0000003f 145 #define NVE4_COMPUTE_UNK0248_UNK0__SHIFT 0 146 #define NVE4_COMPUTE_UNK0248_UNK8__MASK 0x00ffff00 147 #define NVE4_COMPUTE_UNK0248_UNK8__SHIFT 8 148 149 #define NVE4_COMPUTE_UNK0274 0x00000274 150 151 #define NVE4_COMPUTE_UNK0278 0x00000278 152 153 #define NVE4_COMPUTE_UNK027C 0x0000027c 154 155 #define NVE4_COMPUTE_UNK0280 0x00000280 156 157 #define NVE4_COMPUTE_UNK0284 0x00000284 158 159 #define NVE4_COMPUTE_UNK0288 0x00000288 160 161 #define NVE4_COMPUTE_UNK0290 0x00000290 162 163 #define NVE4_COMPUTE_UNK02B0 0x000002b0 164 165 #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS 0x000002b4 166 #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS__SHR 8 167 168 #define NVE4_COMPUTE_UNK02B8 0x000002b8 169 170 #define NVE4_COMPUTE_LAUNCH 0x000002bc 171 172 #define NVE4_COMPUTE_MP_TEMP_SIZE(i0) (0x000002e4 + 0xc*(i0)) 173 #define NVE4_COMPUTE_MP_TEMP_SIZE__ESIZE 0x0000000c 174 #define NVE4_COMPUTE_MP_TEMP_SIZE__LEN 0x00000002 175 176 #define NVE4_COMPUTE_MP_TEMP_SIZE_HIGH(i0) (0x000002e4 + 0xc*(i0)) 177 178 #define NVE4_COMPUTE_MP_TEMP_SIZE_LOW(i0) (0x000002e8 + 0xc*(i0)) 179 180 #define NVE4_COMPUTE_MP_TEMP_SIZE_MASK(i0) (0x000002ec + 0xc*(i0)) 181 182 #define NVE4_COMPUTE_UNK0310 0x00000310 183 184 #define NVE4_COMPUTE_FIRMWARE(i0) (0x00000500 + 0x4*(i0)) 185 #define NVE4_COMPUTE_FIRMWARE__ESIZE 0x00000004 186 #define NVE4_COMPUTE_FIRMWARE__LEN 0x00000020 187 188 #define NVE4_COMPUTE_LOCAL_BASE 0x0000077c 189 190 #define NVE4_COMPUTE_TEMP_ADDRESS_HIGH 0x00000790 191 192 #define NVE4_COMPUTE_TEMP_ADDRESS_LOW 0x00000794 193 194 #define NVE4_COMPUTE_UNK0D94 0x00000d94 195 196 #define NVE4_COMPUTE_WATCHDOG_TIMER 0x00000de4 197 198 #define NVE4_COMPUTE_UNK0F44(i0) (0x00000f44 + 0x4*(i0)) 199 #define NVE4_COMPUTE_UNK0F44__ESIZE 0x00000004 200 #define NVE4_COMPUTE_UNK0F44__LEN 0x00000004 201 202 #define NVE4_COMPUTE_UNK1040(i0) (0x00001040 + 0x4*(i0)) 203 #define NVE4_COMPUTE_UNK1040__ESIZE 0x00000004 204 #define NVE4_COMPUTE_UNK1040__LEN 0x0000000c 205 206 #define NVE4_COMPUTE_UNK1288_TIC_FLUSH 0x00001288 207 208 #define NVE4_COMPUTE_TSC_FLUSH 0x00001330 209 #define NVE4_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001 210 #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__MASK 0x03fffff0 211 #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__SHIFT 4 212 213 #define NVE4_COMPUTE_TIC_FLUSH 0x00001334 214 #define NVE4_COMPUTE_TIC_FLUSH_SPECIFIC 0x00000001 215 #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__MASK 0x03fffff0 216 #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4 217 218 #define NVE4_COMPUTE_TEX_CACHE_CTL 0x00001338 219 #define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0 0x00000001 220 #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0 221 #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT 4 222 223 #define NVE4_COMPUTE_UNK1424_TSC_FLUSH 0x00001424 224 225 #define NVE4_COMPUTE_COND_ADDRESS_HIGH 0x00001550 226 227 #define NVE4_COMPUTE_COND_ADDRESS_LOW 0x00001554 228 229 #define NVE4_COMPUTE_COND_MODE 0x00001558 230 #define NVE4_COMPUTE_COND_MODE_NEVER 0x00000000 231 #define NVE4_COMPUTE_COND_MODE_ALWAYS 0x00000001 232 #define NVE4_COMPUTE_COND_MODE_RES_NON_ZERO 0x00000002 233 #define NVE4_COMPUTE_COND_MODE_EQUAL 0x00000003 234 #define NVE4_COMPUTE_COND_MODE_NOT_EQUAL 0x00000004 235 236 #define NVE4_COMPUTE_TSC_ADDRESS_HIGH 0x0000155c 237 238 #define NVE4_COMPUTE_TSC_ADDRESS_LOW 0x00001560 239 240 #define NVE4_COMPUTE_TSC_LIMIT 0x00001564 241 242 #define NVE4_COMPUTE_TIC_ADDRESS_HIGH 0x00001574 243 244 #define NVE4_COMPUTE_TIC_ADDRESS_LOW 0x00001578 245 246 #define NVE4_COMPUTE_TIC_LIMIT 0x0000157c 247 248 #define NVE4_COMPUTE_CODE_ADDRESS_HIGH 0x00001608 249 250 #define NVE4_COMPUTE_CODE_ADDRESS_LOW 0x0000160c 251 252 #define NVE4_COMPUTE_UNK1690 0x00001690 253 254 #define NVE4_COMPUTE_FLUSH 0x00001698 255 #define NVE4_COMPUTE_FLUSH_CODE 0x00000001 256 #define NVE4_COMPUTE_FLUSH_GLOBAL 0x00000010 257 #define NVE4_COMPUTE_FLUSH_CB 0x00001000 258 259 #define NVE4_COMPUTE_UNK1944 0x00001944 260 261 #define NVE4_COMPUTE_DELAY 0x00001a24 262 263 #define NVE4_COMPUTE_UNK1A2C(i0) (0x00001a2c + 0x4*(i0)) 264 #define NVE4_COMPUTE_UNK1A2C__ESIZE 0x00000004 265 #define NVE4_COMPUTE_UNK1A2C__LEN 0x00000005 266 267 #define NVE4_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00 268 269 #define NVE4_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04 270 271 #define NVE4_COMPUTE_QUERY_SEQUENCE 0x00001b08 272 273 #define NVE4_COMPUTE_QUERY_GET 0x00001b0c 274 #define NVE4_COMPUTE_QUERY_GET_MODE__MASK 0x00000003 275 #define NVE4_COMPUTE_QUERY_GET_MODE__SHIFT 0 276 #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE 0x00000000 277 #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE_INTR_NRHOST 0x00000003 278 #define NVE4_COMPUTE_QUERY_GET_INTR 0x00100000 279 #define NVE4_COMPUTE_QUERY_GET_SHORT 0x10000000 280 281 #define NVE4_COMPUTE_TEX_CB_INDEX 0x00002608 282 283 #define NVE4_COMPUTE_UNK260C 0x0000260c 284 285 #define NVE4_COMPUTE_MP_PM_SET(i0) (0x0000335c + 0x4*(i0)) 286 #define NVE4_COMPUTE_MP_PM_SET__ESIZE 0x00000004 287 #define NVE4_COMPUTE_MP_PM_SET__LEN 0x00000008 288 289 #define NVE4_COMPUTE_MP_PM_A_SIGSEL(i0) (0x0000337c + 0x4*(i0)) 290 #define NVE4_COMPUTE_MP_PM_A_SIGSEL__ESIZE 0x00000004 291 #define NVE4_COMPUTE_MP_PM_A_SIGSEL__LEN 0x00000004 292 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_NONE 0x00000000 293 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_USER 0x00000001 294 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LAUNCH 0x00000003 295 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_EXEC 0x00000004 296 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_ISSUE 0x00000005 297 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK11 0x00000011 298 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK14 0x00000014 299 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_UNK1A 0x0000001a 300 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LDST 0x0000001b 301 #define NVE4_COMPUTE_MP_PM_A_SIGSEL_BRANCH 0x0000001c 302 303 #define NVE4_COMPUTE_MP_PM_B_SIGSEL(i0) (0x0000338c + 0x4*(i0)) 304 #define NVE4_COMPUTE_MP_PM_B_SIGSEL__ESIZE 0x00000004 305 #define NVE4_COMPUTE_MP_PM_B_SIGSEL__LEN 0x00000004 306 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_NONE 0x00000000 307 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_WARP 0x00000002 308 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_REPLAY 0x00000008 309 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_TRANSACTION 0x0000000e 310 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_UNK0F 0x0000000f 311 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_L1 0x00000010 312 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_MEM 0x00000011 313 #define NVE4_COMPUTE_MP_PM_B_SIGSEL_UNK13 0x00000013 314 315 #define NVE4_COMPUTE_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0)) 316 #define NVE4_COMPUTE_MP_PM_SRCSEL__ESIZE 0x00000004 317 #define NVE4_COMPUTE_MP_PM_SRCSEL__LEN 0x00000008 318 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__MASK 0x00000003 319 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT 0 320 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__MASK 0x0000001c 321 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT 2 322 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__MASK 0x00000060 323 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT 5 324 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__MASK 0x00000380 325 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT 7 326 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__MASK 0x00000c00 327 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT 10 328 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__MASK 0x00007000 329 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT 12 330 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__MASK 0x00018000 331 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT 15 332 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__MASK 0x000e0000 333 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT 17 334 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__MASK 0x00300000 335 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__SHIFT 20 336 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__MASK 0x01c00000 337 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__SHIFT 22 338 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__MASK 0x06000000 339 #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__SHIFT 25 340 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__MASK 0x38000000 341 #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__SHIFT 27 342 343 #define NVE4_COMPUTE_MP_PM_FUNC(i0) (0x000033bc + 0x4*(i0)) 344 #define NVE4_COMPUTE_MP_PM_FUNC__ESIZE 0x00000004 345 #define NVE4_COMPUTE_MP_PM_FUNC__LEN 0x00000008 346 #define NVE4_COMPUTE_MP_PM_FUNC_MODE__MASK 0x0000000f 347 #define NVE4_COMPUTE_MP_PM_FUNC_MODE__SHIFT 0 348 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP 0x00000000 349 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_PULSE 0x00000001 350 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_B6 0x00000002 351 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK3 0x00000003 352 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6 0x00000004 353 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6_PULSE 0x00000005 354 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK6 0x00000006 355 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK7 0x00000007 356 #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK8 0x00000008 357 #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__MASK 0x000ffff0 358 #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__SHIFT 4 359 360 #define NVE4_COMPUTE_MP_PM_UNK33DC 0x000033dc 361 362 #define NVE4_COMPUTE_LAUNCH_DESC__SIZE 0x00000100 363 #define NVE4_COMPUTE_LAUNCH_DESC_6 0x00000018 364 #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__MASK 0x00000c00 365 #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__SHIFT 10 366 367 #define NVE4_COMPUTE_LAUNCH_DESC_PROG_START 0x00000020 368 369 #define NVE4_COMPUTE_LAUNCH_DESC_12 0x00000030 370 #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__MASK 0x7fffffff 371 #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__SHIFT 0 372 373 #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ 0x00000034 374 #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__MASK 0x0000ffff 375 #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__SHIFT 0 376 #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__MASK 0xffff0000 377 #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__SHIFT 16 378 379 #define NVE4_COMPUTE_LAUNCH_DESC_17 0x00000044 380 #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__MASK 0x0000ffff 381 #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__SHIFT 0 382 383 #define NVE4_COMPUTE_LAUNCH_DESC_18 0x00000048 384 #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__MASK 0xffff0000 385 #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__SHIFT 16 386 387 #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ 0x0000004c 388 #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__MASK 0x0000ffff 389 #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__SHIFT 0 390 #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__MASK 0xffff0000 391 #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__SHIFT 16 392 393 #define NVE4_COMPUTE_LAUNCH_DESC_20 0x00000050 394 #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__MASK 0x000000ff 395 #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__SHIFT 0 396 #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__MASK 0x60000000 397 #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__SHIFT 29 398 #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_16K_SHARED_48K_L1 0x20000000 399 #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_32K_SHARED_32K_L1 0x40000000 400 #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_48K_SHARED_16K_L1 0x60000000 401 402 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0(i0) (0x00000074 + 0x8*(i0)) 403 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__ESIZE 0x00000008 404 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__LEN 0x00000008 405 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__MASK 0xffffffff 406 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__SHIFT 0 407 408 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1(i0) (0x00000078 + 0x8*(i0)) 409 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__ESIZE 0x00000008 410 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__LEN 0x00000008 411 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__MASK 0x000000ff 412 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__SHIFT 0 413 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__MASK 0xffff8000 414 #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__SHIFT 15 415 416 #define NVE4_COMPUTE_LAUNCH_DESC_45 0x000000b4 417 #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__MASK 0x000fffff 418 #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__SHIFT 0 419 #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__MASK 0xf8000000 420 #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__SHIFT 27 421 422 #define NVE4_COMPUTE_LAUNCH_DESC_46 0x000000b8 423 #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__MASK 0x000fffff 424 #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__SHIFT 0 425 #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__MASK 0x3f000000 426 #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__SHIFT 24 427 428 #define NVE4_COMPUTE_LAUNCH_DESC_47 0x000000bc 429 #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__MASK 0x000fffff 430 #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__SHIFT 0 431 432 433 #endif /* NVE4_COMPUTE_XML */ 434