| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CondBrFolding.cpp | 119 MachineBasicBlock *NewDest);
219 MachineBasicBlock *NewDest) { in replaceBrDest() argument
226 .addMBB(NewDest).addImm(MBBInfo->BranchCode); in replaceBrDest()
227 MBBInfo->TBB = NewDest; in replaceBrDest()
232 .addMBB(NewDest); in replaceBrDest()
233 MBBInfo->FBB = NewDest; in replaceBrDest()
236 fixPHIsInSucc(NewDest, OrigDest, MBB); in replaceBrDest()
238 MBB->addSuccessor(NewDest); in replaceBrDest()
239 setBranchProb(MBB, NewDest, MBPI->getEdgeProbability(MBB, OrigDest)); in replaceBrDest()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.h | 37 MachineBasicBlock *NewDest) const override;
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| D | Thumb2InstrInfo.cpp | 50 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
54 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
68 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
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| D | ARMConstantIslandPass.cpp | 1749 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); in fixupConditionalBr() local
1750 if (isBBInRange(MI, NewDest, Br.MaxDisp)) { in fixupConditionalBr()
1754 MI->getOperand(0).setMBB(NewDest); in fixupConditionalBr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.h | 36 MachineBasicBlock *NewDest) const override;
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| D | Thumb2InstrInfo.cpp | 59 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
63 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
77 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64BranchRelaxation.cpp | 393 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); in fixupConditionalBranch() local
394 if (isBlockInRange(MI, NewDest, in fixupConditionalBranch()
405 MI->getOperand(OpNum).setMBB(NewDest); in fixupConditionalBranch()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.h | 36 MachineBasicBlock *NewDest) const override;
|
| D | Thumb2InstrInfo.cpp | 65 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
69 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
83 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest); in ReplaceTailWithBranchTo()
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| D | ARMConstantIslandPass.cpp | 1682 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); in fixupConditionalBr() local
1683 if (BBUtils->isBBInRange(MI, NewDest, Br.MaxDisp)) { in fixupConditionalBr()
1688 MI->getOperand(0).setMBB(NewDest); in fixupConditionalBr()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | BranchFolding.h | 143 MachineBasicBlock &NewDest);
|
| D | TargetInstrInfo.cpp | 142 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
162 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) in ReplaceTailWithBranchTo()
163 insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL); in ReplaceTailWithBranchTo()
164 MBB->addSuccessor(NewDest); in ReplaceTailWithBranchTo()
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| D | BranchFolding.cpp | 355 MachineBasicBlock &NewDest) { in replaceTailWithBranchTo() argument
371 for (MachineBasicBlock::RegisterMaskPair P : NewDest.liveins()) { in replaceTailWithBranchTo()
384 TII->ReplaceTailWithBranchTo(OldInst, &NewDest); in replaceTailWithBranchTo()
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| /external/llvm/lib/CodeGen/ |
| D | BranchFolding.h | 136 MachineBasicBlock *NewDest);
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| D | TargetInstrInfo.cpp | 107 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
121 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) in ReplaceTailWithBranchTo()
122 InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL); in ReplaceTailWithBranchTo()
123 MBB->addSuccessor(NewDest); in ReplaceTailWithBranchTo()
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| D | BranchFolding.cpp | 429 MachineBasicBlock *NewDest) { in ReplaceTailWithBranchTo() argument
430 TII->ReplaceTailWithBranchTo(OldInst, NewDest); in ReplaceTailWithBranchTo()
432 computeLiveIns(*NewDest); in ReplaceTailWithBranchTo()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | BranchFolding.h | 171 MachineBasicBlock &NewDest);
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| D | TargetInstrInfo.cpp | 132 MachineBasicBlock *NewDest) const { in ReplaceTailWithBranchTo()
152 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest)) in ReplaceTailWithBranchTo()
153 insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL); in ReplaceTailWithBranchTo()
154 MBB->addSuccessor(NewDest); in ReplaceTailWithBranchTo()
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| D | BranchFolding.cpp | 366 MachineBasicBlock &NewDest) { in replaceTailWithBranchTo() argument
382 for (MachineBasicBlock::RegisterMaskPair P : NewDest.liveins()) { in replaceTailWithBranchTo()
395 TII->ReplaceTailWithBranchTo(OldInst, &NewDest); in replaceTailWithBranchTo()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 5184 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarXnor() local
5188 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest) in lowerScalarXnor()
5192 MRI.replaceRegWith(Dest.getReg(), NewDest); in lowerScalarXnor()
5193 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist); in lowerScalarXnor()
5205 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in lowerScalarXnor() local
5212 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
5217 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
5225 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp); in lowerScalarXnor()
5229 MRI.replaceRegWith(Dest.getReg(), NewDest); in lowerScalarXnor()
5233 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist); in lowerScalarXnor()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 5916 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarXnor() local
5920 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest) in lowerScalarXnor()
5924 MRI.replaceRegWith(Dest.getReg(), NewDest); in lowerScalarXnor()
5925 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist); in lowerScalarXnor()
5937 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in lowerScalarXnor() local
5944 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
5949 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
5957 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp); in lowerScalarXnor()
5961 MRI.replaceRegWith(Dest.getReg(), NewDest); in lowerScalarXnor()
5965 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist); in lowerScalarXnor()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsConstantIslandPass.cpp | 1586 MachineBasicBlock *NewDest = in fixupConditionalBr() local
1588 if (isBBInRange(MI, NewDest, Br.MaxDisp)) { in fixupConditionalBr()
1594 MI->getOperand(TargetOperand).setMBB(NewDest); in fixupConditionalBr()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsConstantIslandPass.cpp | 1580 MachineBasicBlock *NewDest = in fixupConditionalBr() local
1582 if (isBBInRange(MI, NewDest, Br.MaxDisp)) { in fixupConditionalBr()
1588 MI->getOperand(TargetOperand).setMBB(NewDest); in fixupConditionalBr()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsConstantIslandPass.cpp | 1607 MachineBasicBlock *NewDest = in fixupConditionalBr() local
1609 if (isBBInRange(MI, NewDest, Br.MaxDisp)) { in fixupConditionalBr()
1614 MI->getOperand(TargetOperand).setMBB(NewDest); in fixupConditionalBr()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 572 MachineBasicBlock *NewDest) const;
|