Searched refs:NewSR (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 660 unsigned NewSR = 0; in split() local
665 NewSR = (DSR == Hexagon::subreg_loreg) ? Hexagon::subreg_hireg in split()
670 if ((MS1.isReg() && NewSR == MS1.getSubReg()) || in split()
671 (MS2.isReg() && NewSR == MS2.getSubReg())) in split()
678 .addReg(DR, RegState::Define, NewSR); in split()
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| D | HexagonBitSimplify.cpp | 170 unsigned NewSR, MachineRegisterInfo &MRI);
172 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
327 unsigned NewSR, MachineRegisterInfo &MRI) { in replaceRegWithSub() argument
336 I->setSubReg(NewSR); in replaceRegWithSub()
343 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) { in replaceSubWithSub() argument
354 I->setSubReg(NewSR); in replaceSubWithSub()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 213 static bool replaceRegWithSub(Register OldR, Register NewR, unsigned NewSR,
216 unsigned NewSR, MachineRegisterInfo &MRI);
369 unsigned NewSR, in replaceRegWithSub() argument
373 if (hasTiedUse(OldR, MRI, NewSR)) in replaceRegWithSub()
380 I->setSubReg(NewSR); in replaceRegWithSub()
386 Register NewR, unsigned NewSR, in replaceSubWithSub() argument
390 if (OldSR != NewSR && hasTiedUse(OldR, MRI, NewSR)) in replaceSubWithSub()
399 I->setSubReg(NewSR); in replaceSubWithSub()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 214 unsigned NewSR, MachineRegisterInfo &MRI);
216 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
369 unsigned NewSR, MachineRegisterInfo &MRI) { in replaceRegWithSub() argument
372 if (hasTiedUse(OldR, MRI, NewSR)) in replaceRegWithSub()
379 I->setSubReg(NewSR); in replaceRegWithSub()
385 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) { in replaceSubWithSub() argument
388 if (OldSR != NewSR && hasTiedUse(OldR, MRI, NewSR)) in replaceSubWithSub()
397 I->setSubReg(NewSR); in replaceSubWithSub()
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