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Searched refs:NumSuccs (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/
DVPlanHCFGBuilder.cpp276 unsigned NumSuccs = TI->getNumSuccessors(); in buildPlainCFG() local
278 if (NumSuccs == 1) { in buildPlainCFG()
282 } else if (NumSuccs == 2) { in buildPlainCFG()
/external/llvm-project/llvm/lib/Transforms/Vectorize/
DVPlanHCFGBuilder.cpp276 unsigned NumSuccs = TI->getNumSuccessors(); in buildPlainCFG() local
278 if (NumSuccs == 1) { in buildPlainCFG()
282 } else if (NumSuccs == 2) { in buildPlainCFG()
/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp147 unsigned NumSuccs = MBB->succ_size(); in runOnMachineFunction() local
176 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp157 unsigned NumSuccs = MBB->succ_size(); in runOnMachineFunction() local
186 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) { in runOnMachineFunction()
DHexagonSubtarget.cpp346 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) { in adjustSchedDependency()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp158 unsigned NumSuccs = MBB->succ_size(); in runOnMachineFunction() local
187 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) { in runOnMachineFunction()
DHexagonSubtarget.cpp417 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) { in adjustSchedDependency()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DScheduleDAG.cpp141 assert(N->NumSuccs < std::numeric_limits<unsigned>::max() && in addPred()
144 ++N->NumSuccs; in addPred()
191 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
193 --N->NumSuccs; in removePred()
395 if (SUnit.NumPreds == 0 && SUnit.NumSuccs == 0) { in VerifyScheduledDAG()
DScheduleDAGPrinter.cpp39 return (Node->NumPreds > 10 || Node->NumSuccs > 10); in isNodeHidden()
DScheduleDAGInstrs.cpp877 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
/external/llvm-project/llvm/lib/CodeGen/
DScheduleDAG.cpp141 assert(N->NumSuccs < std::numeric_limits<unsigned>::max() && in addPred()
144 ++N->NumSuccs; in addPred()
191 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
193 --N->NumSuccs; in removePred()
395 if (SUnit.NumPreds == 0 && SUnit.NumSuccs == 0) { in VerifyScheduledDAG()
DScheduleDAGPrinter.cpp39 return (Node->NumPreds > 10 || Node->NumSuccs > 10); in isNodeHidden()
DScheduleDAGInstrs.cpp881 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
/external/llvm/lib/CodeGen/
DScheduleDAG.cpp99 assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!"); in addPred()
101 ++N->NumSuccs; in addPred()
150 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
152 --N->NumSuccs; in removePred()
387 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { in VerifyScheduledDAG()
DScheduleDAGPrinter.cpp42 return (Node->NumPreds > 10 || Node->NumSuccs > 10); in isNodeHidden()
DScheduleDAGInstrs.cpp995 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h269 unsigned NumSuccs; // # of SDep::Data sucss.
310 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
326 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
341 NodeNum(BoundaryID), NodeQueueId(0), NumPreds(0), NumSuccs(0),
/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNILPSched.cpp89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
97 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNILPSched.cpp89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
97 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1900 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
1907 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
1970 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2016 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2163 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2582 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2803 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2830 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
2846 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp2046 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
2053 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
2114 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2160 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2308 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2727 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2949 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2999 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
3015 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp2043 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
2050 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
2111 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2157 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2305 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2724 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2946 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2996 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
3012 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DScheduleDAG.h267 unsigned NumSuccs = 0; ///< # of SDep::Data sucss. variable
/external/llvm-project/llvm/include/llvm/CodeGen/
DScheduleDAG.h267 unsigned NumSuccs = 0; ///< # of SDep::Data sucss. variable
/external/llvm-project/polly/lib/Analysis/
DScopBuilder.cpp1038 unsigned NumSuccs = RN->isSubRegion() ? 1 : TI->getNumSuccessors(); in propagateInvalidStmtDomains() local
1039 for (unsigned u = 0; u < NumSuccs; u++) { in propagateInvalidStmtDomains()