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Searched refs:OP1 (Results 1 – 25 of 40) sorted by relevance

12

/external/pcre/dist2/src/
Dpcre2_jit_compile.c612 #define OP1(op, dst, dstw, src, srcw) \ macro
2148 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
2149 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -OVECTOR(0)); in init_frame()
2151 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
2165 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
2166 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -common->mark_ptr); in init_frame()
2168 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
2178 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
2179 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -OVECTOR(0)); in init_frame()
2181 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
[all …]
Dpcre2_jit_simd_inc.h225 OP1(SLJIT_MOV, TMP1, 0, SLJIT_IMM, character_to_int32(char1 | bit)); in fast_forward_char_simd()
238 OP1(SLJIT_MOV, TMP1, 0, SLJIT_IMM, character_to_int32(bit != 0 ? bit : char2)); in fast_forward_char_simd()
245 OP1(SLJIT_MOV, TMP2, 0, STR_PTR, 0); in fast_forward_char_simd()
333 OP1(MOV_UCHAR, TMP1, 0, SLJIT_MEM1(STR_PTR), IN_UCHARS(-offset)); in fast_forward_char_simd()
339 OP1(SLJIT_MOV, TMP2, 0, STR_PTR, 0); in fast_forward_char_simd()
379 OP1(SLJIT_MOV, TMP2, 0, TMP1, 0); in fast_requested_char_simd()
380 OP1(SLJIT_MOV, TMP3, 0, STR_PTR, 0); in fast_requested_char_simd()
384 OP1(SLJIT_MOV, TMP1, 0, SLJIT_IMM, character_to_int32(char1 | bit)); in fast_requested_char_simd()
397 OP1(SLJIT_MOV, TMP1, 0, SLJIT_IMM, character_to_int32(bit != 0 ? bit : char2)); in fast_requested_char_simd()
404 OP1(SLJIT_MOV, STR_PTR, 0, TMP2, 0); in fast_requested_char_simd()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-int-log.ll53 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
55 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
68 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
70 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
88 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
90 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
118 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
120 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
186 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
188 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
[all …]
Dsve-fixed-length-int-arith.ll53 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
55 ; CHECK: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
68 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
70 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
88 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
90 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
118 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
120 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
186 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
188 ; CHECK: add [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-int-shifts.ll50 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
52 ; CHECK-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
65 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
67 ; VBITS_GE_512-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
93 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
95 ; VBITS_GE_1024-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
108 ; VBITS_GE_2048-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
110 ; VBITS_GE_2048-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
143 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
145 ; CHECK-NEXT: asr [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-int-compares.ll50 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
52 ; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
67 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
69 ; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
99 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
101 ; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
116 ; VBITS_GE_2048-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
118 ; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
153 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
155 ; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-fp-arith.ll53 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
55 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
68 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
70 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
89 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
91 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
124 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
126 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
157 ; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
159 ; CHECK: fadd [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
[all …]
Dsve-fixed-length-int-minmax.ll48 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
50 ; CHECK-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
63 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
65 ; VBITS_GE_512-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
91 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
93 ; VBITS_GE_1024-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
106 ; VBITS_GE_2048-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
108 ; VBITS_GE_2048-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
139 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
141 ; CHECK-NEXT: smax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-fp-minmax.ll48 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
50 ; CHECK-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
63 ; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
65 ; VBITS_GE_512-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
92 ; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
94 ; VBITS_GE_1024-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
107 ; VBITS_GE_2048-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
109 ; VBITS_GE_2048-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
140 ; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
142 ; CHECK-NEXT: fmaxnm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
[all …]
Dsve-fixed-length-int-div.ll85 ; CHECK-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
88 ; CHECK-NEXT: sunpkhi [[OP1_HI:z[0-9]+]].h, [[OP1]].b
91 ; CHECK-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, [[OP1]].b
119 ; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
122 ; VBITS_GE_512-NEXT: sunpkhi [[OP1_HI:z[0-9]+]].h, [[OP1]].b
125 ; VBITS_GE_512-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, [[OP1]].b
153 ; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
156 ; VBITS_GE_1024-NEXT: sunpkhi [[OP1_HI:z[0-9]+]].h, [[OP1]].b
159 ; VBITS_GE_1024-NEXT: sunpklo [[OP1_LO:z[0-9]+]].h, [[OP1]].b
187 ; VBITS_GE_2048-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
[all …]
Dsve-fixed-length-int-select.ll46 ; CHECK-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
50 ; CHECK-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
66 ; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
70 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
86 ; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
90 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
106 ; VBITS_GE_2048-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
110 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
144 ; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
148 ; CHECK-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
[all …]
Dfp16-v4-instructions.ll7 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
32 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
34 ; CHECK-CVT-NEXT: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
48 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
50 ; CHECK-CVT-NEXT: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
64 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
66 ; CHECK-CVT-NEXT: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
157 ; CHECK-COMMON-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
158 ; CHECK-COMMON-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
[all …]
Dsve-fixed-length-fp-select.ll46 ; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
50 ; CHECK-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
66 ; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
70 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
86 ; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
90 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
106 ; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
110 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
144 ; CHECK-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
148 ; CHECK-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
[all …]
Dfp16-v8-instructions.ll313 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
316 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
325 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
327 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
366 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
369 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
378 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
380 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dsubtract-of-one-hand-of-select.ll15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[FALSEVAL:%.*]], [[OP1:%.*]]
25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[TRUEVAL:%.*]], [[OP1:%.*]]
38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[FALSEVAL:%.*]], [[OP1:%.*]]
53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP1:%.*]], i8 [[FALSEVAL:%.*]]
55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[O]], [[OP1]]
69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[O]], [[OP1:%.*]]
/external/llvm/test/CodeGen/AArch64/
Dfp16-v4-instructions.ll6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
135 ; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
[all …]
Dfp16-v8-instructions.ll288 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
291 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
300 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
302 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
340 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
343 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
352 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
354 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFISelDAGToDAG.cpp264 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
268 SDNode *OP1N = OP1.getNode(); in PreprocessLoad()
284 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
286 dyn_cast<GlobalAddressSDNode>(OP1.getNode())) in PreprocessLoad()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelDAGToDAG.cpp264 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
268 SDNode *OP1N = OP1.getNode(); in PreprocessLoad()
284 SDValue OP1 = LDAddrNode->getOperand(0); in PreprocessLoad() local
286 dyn_cast<GlobalAddressSDNode>(OP1.getNode())) in PreprocessLoad()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]]
7 ; CHECK: lsr([[OP1]],#{{[0-9]+}})
/external/llvm/test/CodeGen/Hexagon/
Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
7 ; CHECK: lsr([[OP1]], #{{[0-9]+}})
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600Defines.h40 OP1 = (1 << 10), enumerator
/external/llvm/lib/Target/AMDGPU/
DR600Defines.h41 OP1 = (1 << 10), enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600Defines.h40 OP1 = (1 << 10), enumerator
/external/rust/crates/quiche/deps/boringssl/src/decrepit/cast/
Dcast.c93 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \ argument
96 t = (key[n * 2] OP1 R) & 0xffffffff; \
102 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \

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