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Searched refs:OP2 (Results 1 – 25 of 36) sorted by relevance

12

/external/llvm-project/llvm/test/Transforms/InstCombine/
Dassoc-cast-assoc.ll7 ; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15
8 ; CHECK-NEXT: ret i5 [[OP2]]
19 ; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
20 ; CHECK-NEXT: ret <2 x i32> [[OP2]]
31 ; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11
32 ; CHECK-NEXT: ret i5 [[OP2]]
43 ; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>
44 ; CHECK-NEXT: ret <2 x i32> [[OP2]]
57 ; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5
58 ; CHECK-NEXT: ret i5 [[OP2]]
[all …]
/external/pcre/dist2/src/
Dpcre2_jit_compile.c614 #define OP2(op, dst, dstw, src1, src1w, src2, src2w) \ macro
3064 OP2(SLJIT_SUB | SLJIT_SET_Z, COUNT_MATCH, 0, COUNT_MATCH, 0, SLJIT_IMM, 1); in count_match()
3074 OP2(SLJIT_SUB, STACK_TOP, 0, STACK_TOP, 0, SLJIT_IMM, size * sizeof(sljit_sw)); in allocate_stack()
3090 OP2(SLJIT_ADD, STACK_TOP, 0, STACK_TOP, 0, SLJIT_IMM, size * sizeof(sljit_sw)); in free_stack()
3122 OP2(SLJIT_SUB, SLJIT_R0, 0, SLJIT_MEM1(SLJIT_S0), SLJIT_OFFSETOF(jit_arguments, begin), SLJIT_IMM, … in reset_ovector()
3136 OP2(SLJIT_SUB | SLJIT_SET_Z, SLJIT_R2, 0, SLJIT_R2, 0, SLJIT_IMM, 1); in reset_ovector()
3145 OP2(SLJIT_ADD, SLJIT_R1, 0, SLJIT_R1, 0, SLJIT_IMM, sizeof(sljit_sw)); in reset_ovector()
3146 OP2(SLJIT_SUB | SLJIT_SET_Z, SLJIT_R2, 0, SLJIT_R2, 0, SLJIT_IMM, 1); in reset_ovector()
3186 OP2(SLJIT_ADD, TMP2, 0, TMP1, 0, SLJIT_IMM, size - uncleared_size); in reset_early_fail()
3190 OP2(SLJIT_ADD, TMP1, 0, TMP1, 0, SLJIT_IMM, 3 * sizeof(sljit_sw)); in reset_early_fail()
[all …]
Dpcre2_jit_simd_inc.h48 OP2(SLJIT_AND, reg, 0, reg, 0, SLJIT_IMM, 0xc0); in jump_if_utf_char_start()
51 OP2(SLJIT_AND, reg, 0, reg, 0, SLJIT_IMM, 0xfc00); in jump_if_utf_char_start()
265 OP2(SLJIT_AND, STR_PTR, 0, STR_PTR, 0, SLJIT_IMM, ~0xf); in fast_forward_char_simd()
266 OP2(SLJIT_AND, TMP2, 0, TMP2, 0, SLJIT_IMM, 0xf); in fast_forward_char_simd()
279 OP2(SLJIT_ADD, STR_PTR, 0, STR_PTR, 0, TMP2, 0); in fast_forward_char_simd()
280 OP2(SLJIT_LSHR, TMP1, 0, TMP1, 0, TMP2, 0); in fast_forward_char_simd()
284 OP2(SLJIT_SUB, STR_PTR, 0, STR_PTR, 0, TMP2, 0); in fast_forward_char_simd()
289 OP2(SLJIT_ADD, STR_PTR, 0, STR_PTR, 0, SLJIT_IMM, 16); in fast_forward_char_simd()
316 OP2(SLJIT_ADD, STR_PTR, 0, STR_PTR, 0, TMP1, 0); in fast_forward_char_simd()
322 OP2(SLJIT_SUB | SLJIT_SET_GREATER, SLJIT_UNUSED, 0, STR_PTR, 0, STR_END, 0); in fast_forward_char_simd()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-int-log.ll54 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
55 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
69 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
70 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
89 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
90 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
119 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
120 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
187 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
188 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d
[all …]
Dsve-fixed-length-int-arith.ll54 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
55 ; CHECK: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
69 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
70 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
89 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
90 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
119 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
120 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
187 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
188 ; CHECK: add [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-int-shifts.ll51 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
52 ; CHECK-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
66 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
67 ; VBITS_GE_512-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
94 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
95 ; VBITS_GE_1024-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
109 ; VBITS_GE_2048-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
110 ; VBITS_GE_2048-NEXT: asr [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
144 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
145 ; CHECK-NEXT: asr [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-int-compares.ll51 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
52 ; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
68 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
69 ; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
100 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
101 ; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
117 ; VBITS_GE_2048-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
118 ; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
154 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
155 ; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-fp-arith.ll54 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
55 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
69 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
70 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
90 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
91 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
125 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
126 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
158 ; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
159 ; CHECK: fadd [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
[all …]
Dsve-fixed-length-int-minmax.ll49 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
50 ; CHECK-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
64 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
65 ; VBITS_GE_512-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
92 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
93 ; VBITS_GE_1024-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
107 ; VBITS_GE_2048-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
108 ; VBITS_GE_2048-NEXT: smax [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
140 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
141 ; CHECK-NEXT: smax [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-fp-minmax.ll49 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
50 ; CHECK-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
64 ; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
65 ; VBITS_GE_512-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
93 ; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
94 ; VBITS_GE_1024-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
108 ; VBITS_GE_2048-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
109 ; VBITS_GE_2048-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
141 ; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
142 ; CHECK-NEXT: fmaxnm [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
[all …]
Dsve-fixed-length-int-div.ll86 ; CHECK-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
89 ; CHECK-NEXT: sunpkhi [[OP2_HI:z[0-9]+]].h, [[OP2]].b
90 ; CHECK-NEXT: sunpklo [[OP2_LO:z[0-9]+]].h, [[OP2]].b
120 ; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
123 ; VBITS_GE_512-NEXT: sunpkhi [[OP2_HI:z[0-9]+]].h, [[OP2]].b
124 ; VBITS_GE_512-NEXT: sunpklo [[OP2_LO:z[0-9]+]].h, [[OP2]].b
154 ; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
157 ; VBITS_GE_1024-NEXT: sunpkhi [[OP2_HI:z[0-9]+]].h, [[OP2]].b
158 ; VBITS_GE_1024-NEXT: sunpklo [[OP2_LO:z[0-9]+]].h, [[OP2]].b
188 ; VBITS_GE_2048-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-int-select.ll47 ; CHECK-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
50 ; CHECK-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
67 ; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
70 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
87 ; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
90 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
107 ; VBITS_GE_2048-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
110 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
145 ; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
148 ; CHECK-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
[all …]
Dsve-fixed-length-fp-select.ll47 ; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
50 ; CHECK-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
67 ; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
70 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
87 ; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
90 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
107 ; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
110 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
145 ; CHECK-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
148 ; CHECK-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
[all …]
Dfp16-v4-instructions.ll8 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
33 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
34 ; CHECK-CVT-NEXT: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
49 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
50 ; CHECK-CVT-NEXT: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
65 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
66 ; CHECK-CVT-NEXT: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
158 ; CHECK-COMMON-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
159 ; CHECK-FP16-NEXT: scvtf v0.4h, [[OP2]]
[all …]
Dfp16-v8-instructions.ll314 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
315 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
326 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
328 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
367 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
368 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
379 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
381 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
/external/llvm/test/CodeGen/AArch64/
Dfp16-v4-instructions.ll7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
137 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
[all …]
Dfp16-v8-instructions.ll289 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
290 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
301 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
303 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
341 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
342 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
353 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
355 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]]
6 ; CHECK-NOT: add([[OP0]],#[[OP2]])
/external/llvm/test/CodeGen/Hexagon/
Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
6 ; CHECK-NOT: add([[OP0]], #[[OP2]])
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600Defines.h41 OP2 = (1 << 11), enumerator
/external/llvm/lib/Target/AMDGPU/
DR600Defines.h42 OP2 = (1 << 11), enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600Defines.h41 OP2 = (1 << 11), enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp150 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
/external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp150 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp134 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()

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