| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-fixed-length-fp-arith.ll | 574 ; CHECK-DAG: ld1h { [[OP3:z[0-9]+]].h }, [[PG]]/z, [x2]
575 ; CHECK: fmla [[OP3]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
576 ; CHECK: st1h { [[OP3]].h }, [[PG]], [x0]
591 ; CHECK-DAG: ld1h { [[OP3:z[0-9]+]].h }, [[PG]]/z, [x2]
592 ; CHECK: fmla [[OP3]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
593 ; CHECK: st1h { [[OP3]].h }, [[PG]], [x0]
608 ; CHECK-DAG: ld1h { [[OP3:z[0-9]+]].h }, [[PG]]/z, [x2]
609 ; CHECK: fmla [[OP3]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
610 ; CHECK: st1h { [[OP3]].h }, [[PG]], [x0]
625 ; CHECK-DAG: ld1h { [[OP3:z[0-9]+]].h }, [[PG]]/z, [x2]
[all …]
|
| D | fp16-v4-instructions.ll | 160 ; CHECK-CVT-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
161 ; CHECK-CVT-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
194 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
195 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
196 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
241 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
242 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
243 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
|
| D | fp16-v8-instructions.ll | 327 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
328 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
329 ; CHECK: fcvtn v0.4h, [[OP3]].4s
380 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
381 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
382 ; CHECK: fcvtn v0.4h, [[OP3]].4s
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v4-instructions.ll | 137 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
138 ; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
170 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
171 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
172 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
213 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
214 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
215 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
|
| D | fp16-v8-instructions.ll | 302 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
303 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
304 ; CHECK: fcvtn v0.4h, [[OP3]].4s
354 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
355 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
356 ; CHECK: fcvtn v0.4h, [[OP3]].4s
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 36 OP3 = (1 << 5), enumerator
|
| D | R600InstrInfo.cpp | 144 (TargetFlags & R600_InstFlag::OP3)); in hasInstrModifiers()
1410 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3; in getFlagOp()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 37 OP3 = (1 << 5), enumerator
|
| D | R600InstrInfo.cpp | 136 (TargetFlags & R600_InstFlag::OP3)); in hasInstrModifiers()
1436 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3; in getFlagOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 36 OP3 = (1 << 5), enumerator
|
| D | R600InstrInfo.cpp | 144 (TargetFlags & R600_InstFlag::OP3)); in hasInstrModifiers()
1409 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3; in getFlagOp()
|
| /external/rust/crates/quiche/deps/boringssl/src/decrepit/cast/ |
| D | cast.c | 93 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \ argument
102 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
|
| /external/boringssl/src/decrepit/cast/ |
| D | cast.c | 93 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \ argument
102 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
|
| /external/libevent/ |
| D | whatsnew-2.1.txt | 552 #define OP3 3
|
| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_008.ppm | 1816 ��`OP3!"��>/!nbB�{Znn>mm=}�M^b.%%�-->0!( %
|