Home
last modified time | relevance | path

Searched refs:OpcStr (Results 1 – 25 of 26) sorted by relevance

12

/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td19 class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
25 class VISInstID<bits<9> opfval, string OpcStr>
28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
37 class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
40 !strconcat(OpcStr, " $rs1, $rd"), []>;
44 class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
47 !strconcat(OpcStr, " $rs2, $rd"), []>;
51 class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
54 !strconcat(OpcStr, " $rd"), []>;
DSparcInstr64Bit.td350 multiclass BranchOnReg<bits<3> cond, string OpcStr> {
352 !strconcat(OpcStr, " $rs1, $imm16"), []>;
354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
361 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
364 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
383 multiclass MOVR< bits<3> rcond, string OpcStr> {
386 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
[all …]
DSparcInstrInfo.td288 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
293 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
298 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
305 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
308 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
312 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
317 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
321 !strconcat(OpcStr, " [$addr], $dst"),
326 !strconcat(OpcStr, " [$addr], $dst"),
333 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
[all …]
DSparcInstrFormats.td227 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
231 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrVIS.td18 class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
24 class VISInstID<bits<9> opfval, string OpcStr>
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
36 class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
43 class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
46 !strconcat(OpcStr, " $rs2, $rd"), []>;
50 class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
53 !strconcat(OpcStr, " $rd"), []>;
DSparcInstr64Bit.td349 multiclass BranchOnReg<bits<3> cond, string OpcStr> {
351 !strconcat(OpcStr, " $rs1, $imm16"), []>;
353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
360 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
363 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
382 multiclass MOVR< bits<3> rcond, string OpcStr> {
385 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
[all …]
DSparcInstrInfo.td308 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
313 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
318 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
325 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
328 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
332 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
337 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
341 !strconcat(OpcStr, " [$addr], $dst"),
346 !strconcat(OpcStr, " [$addr], $dst"),
353 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
[all …]
DSparcInstrFormats.td226 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
230 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
234 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrVIS.td18 class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
24 class VISInstID<bits<9> opfval, string OpcStr>
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
36 class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
43 class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
46 !strconcat(OpcStr, " $rs2, $rd"), []>;
50 class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
53 !strconcat(OpcStr, " $rd"), []>;
DSparcInstr64Bit.td349 multiclass BranchOnReg<bits<3> cond, string OpcStr> {
351 !strconcat(OpcStr, " $rs1, $imm16"), []>;
353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
360 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
363 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
382 multiclass MOVR< bits<3> rcond, string OpcStr> {
385 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
[all …]
DSparcInstrInfo.td308 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
313 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
318 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
325 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
328 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
332 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
337 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
341 !strconcat(OpcStr, " [$addr], $dst"),
346 !strconcat(OpcStr, " [$addr], $dst"),
353 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
[all …]
DSparcInstrFormats.td226 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
230 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
234 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreInstrInfo.td213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
215 !strconcat(OpcStr, " $dst, $b, $c"),
218 !strconcat(OpcStr, " $dst, $b, $c"),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
224 !strconcat(OpcStr, " $dst, $b, $c"), []>;
226 !strconcat(OpcStr, " $dst, $b, $c"), []>;
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
232 !strconcat(OpcStr, " $dst, $b, $c"),
235 !strconcat(OpcStr, " $dst, $b, $c"),
239 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
215 !strconcat(OpcStr, " $dst, $b, $c"),
218 !strconcat(OpcStr, " $dst, $b, $c"),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
224 !strconcat(OpcStr, " $dst, $b, $c"), []>;
226 !strconcat(OpcStr, " $dst, $b, $c"), []>;
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
232 !strconcat(OpcStr, " $dst, $b, $c"),
235 !strconcat(OpcStr, " $dst, $b, $c"),
239 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
223 !strconcat(OpcStr, " $dst, $b, $c"),
226 !strconcat(OpcStr, " $dst, $b, $c"),
230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
232 !strconcat(OpcStr, " $dst, $b, $c"), []>;
234 !strconcat(OpcStr, " $dst, $b, $c"), []>;
237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
240 !strconcat(OpcStr, " $dst, $b, $c"),
243 !strconcat(OpcStr, " $dst, $b, $c"),
247 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
[all …]
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td165 // The instructions are named "<OpcStr><Width>" (e.g. "add.s64").
166 multiclass I3<string OpcStr, SDNode OpNode> {
169 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
173 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
177 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
181 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
185 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
189 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
194 // named "<OpcStr>.s32" (e.g. "addc.cc.s32").
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
[all …]
DNVPTXIntrinsics.td328 // We need a full string for OpcStr here because we need to deal with case like
330 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
333 OpcStr,
336 // We need a full string for OpcStr here because we need to deal with the case
338 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
342 OpcStr,
345 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
350 OpcStr,
991 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
994 !strconcat("atom", SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b;"),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td165 // The instructions are named "<OpcStr><Width>" (e.g. "add.s64").
166 multiclass I3<string OpcStr, SDNode OpNode> {
169 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
173 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
177 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
181 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
185 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
189 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
194 // named "<OpcStr>.s32" (e.g. "addc.cc.s32").
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
[all …]
DNVPTXIntrinsics.td328 // We need a full string for OpcStr here because we need to deal with case like
330 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
333 OpcStr,
336 // We need a full string for OpcStr here because we need to deal with the case
338 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
342 OpcStr,
345 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
350 OpcStr,
991 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
994 !strconcat("atom", SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b;"),
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td168 // The instructions are named "<OpcStr><Width>" (e.g. "add.s64").
169 multiclass I3<string OpcStr, SDNode OpNode> {
172 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
176 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
180 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
184 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
188 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
192 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
197 // named "<OpcStr>.s32" (e.g. "addc.cc.s32").
198 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
[all …]
DNVPTXIntrinsics.td160 // We need a full string for OpcStr here because we need to deal with case like
162 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
165 OpcStr,
168 // We need a full string for OpcStr here because we need to deal with the case
170 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
174 OpcStr,
177 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
182 OpcStr,
882 string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
887 !strconcat(OpcStr,
[all …]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td692 string OpcStr, PatFrag OpNode>
696 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)",
710 string OpcStr, PatFrag OpNode>
714 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)",
/external/llvm/docs/
DWritingAnLLVMBackend.rst806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
809 !strconcat(OpcStr, " $b, $c, $dst"),
813 !strconcat(OpcStr, " $b, $c, $dst"),
/external/llvm-project/llvm/docs/
DWritingAnLLVMBackend.rst806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
809 !strconcat(OpcStr, " $b, $c, $dst"),
813 !strconcat(OpcStr, " $b, $c, $dst"),
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td5279 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5280 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5281 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;

12