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Searched refs:PWR (Results 1 – 25 of 32) sorted by relevance

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/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr_ex.c134 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_GetVoltageRange()
138 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) in HAL_PWREx_GetVoltageRange()
148 return (PWR->CR1 & PWR_CR1_VOS); in HAL_PWREx_GetVoltageRange()
190 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_ControlVoltageScaling()
193 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
196 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); in HAL_PWREx_ControlVoltageScaling()
200 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
213 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
219 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_ControlVoltageScaling()
[all …]
Dstm32l4xx_hal_pwr.c123 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_EnableBkUpAccess()
133 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_DisableBkUpAccess()
335 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); in HAL_PWR_ConfigPVD()
376 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
385 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
414 …MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SH… in HAL_PWR_EnableWakeUpPin()
417 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
433 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); in HAL_PWR_DisableWakeUpPin()
471 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWR_EnterSLEEPMode()
481 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) in HAL_PWR_EnterSLEEPMode()
[all …]
Dstm32l4xx_hal_rcc.c683 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCC_OscConfig()
686 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_RCC_OscConfig()
691 while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCC_OscConfig()
Dstm32l4xx_hal_rcc_ex.c340 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_RCCEx_PeriphCLKConfig()
345 while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) in HAL_RCCEx_PeriphCLKConfig()
2493 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCCEx_EnableLSCO()
2526 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCCEx_DisableLSCO()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr_ex.c134 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_GetVoltageRange()
138 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) in HAL_PWREx_GetVoltageRange()
148 return (PWR->CR1 & PWR_CR1_VOS); in HAL_PWREx_GetVoltageRange()
190 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_ControlVoltageScaling()
193 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
196 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); in HAL_PWREx_ControlVoltageScaling()
200 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
213 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
219 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) in HAL_PWREx_ControlVoltageScaling()
[all …]
Dstm32l4xx_hal_pwr.c123 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_EnableBkUpAccess()
133 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_DisableBkUpAccess()
335 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); in HAL_PWR_ConfigPVD()
376 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
385 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
414 …MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SH… in HAL_PWR_EnableWakeUpPin()
417 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
433 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); in HAL_PWR_DisableWakeUpPin()
471 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWR_EnterSLEEPMode()
481 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) in HAL_PWR_EnterSLEEPMode()
[all …]
Dstm32l4xx_hal_rcc.c683 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCC_OscConfig()
686 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_RCC_OscConfig()
691 while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCC_OscConfig()
Dstm32l4xx_hal_rcc_ex.c340 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_RCCEx_PeriphCLKConfig()
345 while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) in HAL_RCCEx_PeriphCLKConfig()
2493 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCCEx_EnableLSCO()
2526 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) in HAL_RCCEx_DisableLSCO()
/external/llvm/test/CodeGen/PowerPC/
Dcode-align.ll2 ; RUN: llc -mcpu=970 < %s | FileCheck %s -check-prefix=PWR
6 ; RUN: llc -mcpu=pwr4 < %s | FileCheck %s -check-prefix=PWR
7 ; RUN: llc -mcpu=pwr5 < %s | FileCheck %s -check-prefix=PWR
8 ; RUN: llc -mcpu=pwr5x < %s | FileCheck %s -check-prefix=PWR
9 ; RUN: llc -mcpu=pwr6 < %s | FileCheck %s -check-prefix=PWR
10 ; RUN: llc -mcpu=pwr6x < %s | FileCheck %s -check-prefix=PWR
11 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR
12 ; RUN: llc -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR
24 ; PWR-LABEL: .globl foo
27 ; PWR: .p2align 4
[all …]
Dmachine-combiner.ll1 …3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR
98 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
99 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
100 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
101 ; CHECK-PWR: # kill
116 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
117 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
118 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
119 ; CHECK-PWR: # kill
134 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dmachine-combiner.ll1 …erify-machineinstrs -O3 -mcpu=pwr7 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR
95 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
96 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
97 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
109 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
110 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
111 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
123 ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
124 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
125 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
[all …]
Dcode-align.ll2 ; RUN: llc -verify-machineinstrs -mcpu=970 < %s | FileCheck %s -check-prefixes=CHECK,PWR
6 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 < %s | FileCheck %s -check-prefixes=CHECK,PWR
7 ; RUN: llc -verify-machineinstrs -mcpu=pwr5 < %s | FileCheck %s -check-prefixes=CHECK,PWR
8 ; RUN: llc -verify-machineinstrs -mcpu=pwr5x < %s | FileCheck %s -check-prefixes=CHECK,PWR
9 ; RUN: llc -verify-machineinstrs -mcpu=pwr6 < %s | FileCheck %s -check-prefixes=CHECK,PWR
10 ; RUN: llc -verify-machineinstrs -mcpu=pwr6x < %s | FileCheck %s -check-prefixes=CHECK,PWR
11 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefixes=CHECK,PWR
12 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s -check-prefixes=CHECK,PWR
25 ; PWR: .p2align 4
38 ; PWR: .p2align 4
[all …]
Dloop-align.ll3 …trs -mcpu=pwr8 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
4 …trs -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
5 …nstrs -mcpu=pwr8 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
6 …nstrs -mcpu=pwr9 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
10 …le powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMO…
11 …le powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMO…
12 …iple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMO…
13 …iple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMO…
70 ; PWR: .p2align 5
72 ; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
[all …]
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_pwr.h209 (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
210 (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
231 (PWR->SCR = (__FLAG__)) :\
232 (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
Dstm32l4xx_hal_pwr_ex.h689 … MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
691 … tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_pwr.h209 (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
210 (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
231 (PWR->SCR = (__FLAG__)) :\
232 (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
Dstm32l4xx_hal_pwr_ex.h689 … MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
691 … tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
/external/pffft/
Dtest_pffft.cpp57 #define PWR2LOG(PWR) ((PWR) < 1E-30 ? 10.0 * log10(1E-30) : 10.0 * log10(PWR)) argument
Dtest_pffft.c72 #define PWR2LOG(PWR) ( (PWR) < 1E-30 ? 10.0*log10(1E-30) : 10.0*log10(PWR) ) argument
/external/perfetto/src/traced/probes/ftrace/test/data/android_seed_N2F62_3.10.49/events/kgsl/kgsl_context_create/
Dformat15 …_TS" }, { 0x00000080, "USER_TS" }, { 0x00000200, "NO_FT" }, { 0x00000800, "PWR" }, { 0x00000001, "…
/external/perfetto/src/traced/probes/ftrace/test/data/android_walleye_OPM5.171019.017.A1_4.4.88/events/kgsl/kgsl_context_create/
Dformat15 …00000200, "NO_FT" }, { 0x10000000, "INVALIDATE_ON_FAULT" }, { 0x00000800, "PWR" }, { 0x00000001, "…
/external/toybox/lib/
Dportability.c444 SIGNIFY(PWR),
/external/pigweed/pw_log/
Ddocs.rst346 module, like ``"BLE"``, ``"PWR"``, ``"BAT"`` and so on. Thus, adding the
/external/cpuinfo/test/dmesg/
Dzenfone-2.log1211 [ 4.030522] HACK - Before PWR ON - pwr_mask read: reg=0x3f pwr_mask=0x3c3f3ff
1229 [ 4.030798] HACK - PR: After PWR ON - pwr_mask read: reg=0x3f pwr_mask=0xc3f3c0
Dgalaxy-a3-2016-eu.log393 <6>[ 2.318530] [0: swapper/0: 1] PWR key is released

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