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Searched refs:Pg (Results 1 – 25 of 56) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
D	sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll	7 ; PRFB <prfop>, <Pg>, [<Xn\|SP>, <Zm>.S, <mod>] -> 32-bit indexes 8 define void @llvm_aarch64_sve_prfb_gather_uxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsc… 12 …call void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsca… 16 define void @llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, i8* %bas… 20 …call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsca… 24 ; PRFB <prfop>, <Pg>, [<Xn\|SP>, <Zm>.D, <mod>] -> 32-bit unpacked indexes 26 define void @llvm_aarch64_sve_prfb_gather_uxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vsc… 30 …call void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vsca… 34 define void @llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, i8* %bas… 38 …call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vsca… [all …]
D	sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll	7 ; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element 8 …_sve_prfb_gather_scalar_offset_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind { 12 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x… 16 ; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element 17 …_sve_prfb_gather_scalar_offset_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind { 21 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x… 25 ; PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element 26 …_sve_prfh_gather_scalar_offset_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind { 30 …call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x… 34 ; PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element [all …]
D	sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll	7 ; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 1, ..., 31 8 …et_nx4vi32_runtime_offset(<vscale x 4 x i32> %bases, i64 %offset, <vscale x 4 x i1> %Pg) nounwind { 12 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x… 16 …2_invalid_immediate_offset_upper_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind { 21 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x… 25 …2_invalid_immediate_offset_lower_bound(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind { 30 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x… 34 ; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 1, ..., 31 35 …et_nx2vi64_runtime_offset(<vscale x 2 x i64> %bases, i64 %offset, <vscale x 2 x i1> %Pg) nounwind { 39 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx2vi64(<vscale x 2 x i1> %Pg, <vscale x 2 x… [all …]
D	sve-pred-log.ll	7 define <vscale x 16 x i1> @vselect_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 … 11 %res = select <vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd 15 define <vscale x 8 x i1> @vselect_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1>… 19 %res = select <vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd 23 define <vscale x 4 x i1> @vselect_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1>… 27 %res = select <vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd 31 define <vscale x 2 x i1> @vselect_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1>… 35 %res = select <vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd 39 define <vscale x 16 x i1> @and_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1… 43 …%res = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 1… [all …]
D	sve-intrinsics-ldN-reg+reg-addr-mode.ll	8 define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 %addr, i64 %a) { 13 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… 18 define <vscale x 16 x i16> @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 %addr, i64 %a) { 23 %res = call <vscale x 16 x i16> @llvm.aarch64.sve.ld2.nxv16i16.nxv8i1.p0i16(<vscale x 8 x i1> %Pg, … 27 define <vscale x 16 x half> @ld2.nxv16f16(<vscale x 8 x i1> %Pg, half %addr, i64 %a) { 32 %res = call <vscale x 16 x half> @llvm.aarch64.sve.ld2.nxv16f16.nxv8i1.p0f16(<vscale x 8 x i1> %Pg,… 36 define <vscale x 16 x bfloat> @ld2.nxv16bf16(<vscale x 8 x i1> %Pg, bfloat %addr, i64 %a) #0 { 41 …x 16 x bfloat> @llvm.aarch64.sve.ld2.nxv16bf16.nxv8i1.p0bf16(<vscale x 8 x i1> %Pg, bfloat %addr2) 46 define <vscale x 8 x i32> @ld2.nxv8i32(<vscale x 4 x i1> %Pg, i32 %addr, i64 %a) { 51 %res = call <vscale x 8 x i32> @llvm.aarch64.sve.ld2.nxv8i32.nxv4i1.p0i32(<vscale x 4 x i1> %Pg, i3… [all …]
D	sve-intrinsics-ldN-reg+imm-addr-mode.ll	14 define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> %addr) { 20 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… 24 define <vscale x 32 x i8> @ld2.nxv32i8_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> %add… 30 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… 34 define <vscale x 32 x i8> @ld2.nxv32i8_upper_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%add… 40 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… 44 define <vscale x 32 x i8> @ld2.nxv32i8_not_multiple_of_2(<vscale x 16 x i1> %Pg, <vscale x 16 x i8>… 51 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… 55 define <vscale x 32 x i8> @ld2.nxv32i8_outside_lower_bound(<vscale x 16 x i1> %Pg, <vscale x 16 x i… 62 %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %Pg, i… [all …]
D	aarch64-sve-asm.ll	`56 define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscal… 57 …alf> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half>… 67 define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn) { 68 …%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscal…`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	SVEInstrFormats.td	`402 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), 403 asm, "\t$Pg, $Pn", 406 bits<4> Pg; 413 let Inst{13-10} = Pg; 423 : I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn), 424 asm, "\t$Pdn, $Pg, $_Pdn", 428 bits<4> Pg; 435 let Inst{8-5} = Pg; 467 : I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn), 468 asm, "\t$Rdn, $Pg", [all …]`
D	AArch64SVEInstrInfo.td	1010 def : InstAlias<"mov $Pd, $Pg/m, $Pn", 1011 (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>; 1014 def : InstAlias<"mov $Pd, $Pg/z, $Pn", 1015 (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>; 1019 def : InstAlias<"movs $Pd, $Pg/z, $Pn", 1020 (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>; 1022 def : InstAlias<"not $Pd, $Pg/z, $Pn", 1023 (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>; 1025 def : InstAlias<"nots $Pd, $Pg/z, $Pn", 1026 (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>; [all …]
/external/llvm-project/llvm/lib/Target/AArch64/
D	SVEInstrFormats.td	`422 : Pat<(vt (op pt:$Pg, vt:$Src, inreg_vt, vt:$PassThru)), 423 (inst $PassThru, $Pg, $Src)>; 428 : Pat<(vt (op pt:$Pg, vt:$Rn, (vt (AArch64dup (it (cast i32:$imm)))))), 429 (inst $Pg, $Rn, i32:$imm)>; 483 Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> { 490 Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> { 518 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), 519 asm, "\t$Pg, $Pn", 522 bits<4> Pg; 529 let Inst{13-10} = Pg; [all …]`
D	AArch64SVEInstrInfo.td	1458 def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 PPR:$Pg), (nxv2f16 ZPR:$Zs), (nxv2f32 ZPR:$Zd))), 1459 (FCVT_ZPmZ_HtoS ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; 1463 …def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 PPR:$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 Z… 1464 (FCVT_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; 1467 def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), 1469 (SCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; 1471 def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 PPR:$Pg), 1473 (SCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; 1475 def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), 1477 (SCVTF_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; [all …]
/external/pdfium/testing/resources/
D	tagged_alt_text.in	`124 /Pg 3 0 R 133 /Pg 3 0 R 143 /Pg 3 0 R`
D	hint_table_102p.bin	32 ��*��=I�Pg`K�8�K��JI+1a@=J`��$XI��Mm��#��J@�1�n�y
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
D	AArch64GenAsmWriter.inc	17394 // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117 17410 // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 130 17505 // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 202 17510 // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 206 17515 // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 210 17520 // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 214 17525 // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 218 17531 // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 223 17537 // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 228 17543 // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 233 [all …]
D	AArch64GenAsmWriter1.inc	18115 // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117 18131 // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 130 18226 // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 202 18231 // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 206 18236 // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 210 18241 // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 214 18246 // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 218 18252 // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 223 18258 // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 228 18264 // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 233 [all …]
D	AArch64GenMCCodeEmitter.inc	`5548 // op: Pg 5573 // op: Pg 5591 // op: Pg 5681 // op: Pg 5720 // op: Pg 5760 // op: Pg 5797 // op: Pg 5820 // op: Pg 6002 // op: Pg 6023 // op: Pg [all …]`
/external/vixl/src/aarch64/
D	assembler-sve-aarch64.cc	2024 Emit(DECP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in decp() 2049 Emit(INCP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in incp() 2088 Emit(SQDECP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in sqdecp() 2127 Emit(SQINCP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in sqincp() 2152 Emit(UQDECP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in uqdecp() 2176 Emit(UQINCP_z_p_z \| SVESize(zdn) \| Rd(zdn) \| Pg<8, 5>(pg)); in uqincp() 3553 Emit(CPY_z_p_i \| m \| sh \| SVESize(zd) \| Rd(zd) \| Pg<19, 16>(pg) \| in cpy() 3566 Emit(FCPY_z_p_i \| SVESize(zd) \| Rd(zd) \| Pg<19, 16>(pg) \| imm_field); in fcpy() 5290 Emit(BRKA_p_p_p \| Pd(pd) \| Pg<13, 10>(pg) \| m \| Pn(pn)); in brka() 5299 Emit(BRKAS_p_p_p_z \| Pd(pd) \| Pg<13, 10>(pg) \| Pn(pn)); in brkas() [all …]
/external/python/cryptography/vectors/cryptography_vectors/x509/PKITS_data/smime/
D	SignedInvalidRFC822nameConstraintsTest26.eml	`51 Pg+qsgo4kElvXvInxXNc7ZJH8UC1WfKbryDd4L0CAwEAAaOBljCBkzAfBgNVHSME`
D	SignedValidDNnameConstraintsTest18.eml	`72 O6bhhoH7Ir0jMD+Pg+vQjgXI4Lpl0k13KsUBTvLkb95POIzbZgS6OPNt7k/tfUYB`
/external/ImageMagick/PerlMagick/t/reference/filter/
D	Resize.miff	15 …9�<1�C7�98�67�84�9;�=;�=-�7"�B8�W\�^Ln�Ls�UMU<24*`yBn�Mj�Mr�Mt�Vh^Oi_Oh^Pj`Pg]Jg^F_YBKH5IO>WWH�OJ�…
D	Normalize.miff	`193 ��-#�{\|�cr�;[�D�4(;V�=o�Ul�Wd�Jg�Jh�Pg�Ip�T��t��A-A-A-A-A-B+A.7.D:;UCRRHVV_�lw�lĬ]d�…`
D	Sharpen.miff	18 …<5�E?�+ �%#�&#�/$�7�5�-�FB�i`�:+�2�3�?3�MM�JK�EG�Tb�@a�Eu�R��[��Pr�D\�Pg�#��…
D	GaussianBlur.miff	`15 …8�:6�96�75�63�61�5/�3.�4/�73�?=�IM�Q\�Pb�L\�JP�PFl_DfrIi�Nl�Rn�To�To�Tm�Rj�Pg�Oc~MQH9UJ<YN@^SHbXVf…`
/external/ImageMagick/PerlMagick/t/reference/write/filter/
D	SigmoidalContrast.miff	`43 …Pg�Vj�^g�cp�qq�qc�_FQ:/001+55/861;61>83=81=71?6/=4+;2(:1:13/'0,&0+&3.'93'A4'G8)H7,C3+=1(81(43?…`
D	Wave.miff	43 …Pg�@>�7C�>C�>C�BF�M]�d��QXyE9�<3�;,�6&�:$�=(�<1�>2�A4�C2�B1�?8�?=�?7w=2�:4�AA�PM�UIh`D�iN�XT�>G�CG…

12 3

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