| /external/clang/test/SemaCXX/ |
| D | overloaded-operator.cpp | 110 struct PostInc { struct
111 PostInc operator++(int);
112 PostInc& operator++();
120 void incdec_test(PostInc pi, PostDec pd) { in incdec_test()
121 const PostInc& pi1 = pi++; in incdec_test()
123 PostInc &pi2 = ++pi; in incdec_test()
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| /external/llvm-project/clang/test/SemaCXX/ |
| D | overloaded-operator.cpp | 110 struct PostInc { struct
111 PostInc operator++(int);
112 PostInc& operator++();
120 void incdec_test(PostInc pi, PostDec pd) { in incdec_test()
121 const PostInc& pi1 = pi++; in incdec_test()
123 PostInc &pi2 = ++pi; in incdec_test()
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| D | diagnose_if.cpp | 464 struct PostInc { struct
470 PostInc{}++; in runPostInc()
471 PostInc{}.operator++(1); // expected-warning{{oh no}} in runPostInc()
472 PostInc{}.operator++(2); // expected-error{{oh no}} in runPostInc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 42 PostInc = 6 // Post increment addressing mode enumerator
|
| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 37 PostInc = 6 // Post increment addressing mode enumerator
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 90 PostInc = 6 // Post increment addressing mode enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepInstrInfo.td | 8769 let addrMode = PostInc;
8781 let addrMode = PostInc;
8794 let addrMode = PostInc;
8807 let addrMode = PostInc;
8819 let addrMode = PostInc;
8857 let addrMode = PostInc;
8869 let addrMode = PostInc;
8882 let addrMode = PostInc;
8895 let addrMode = PostInc;
8907 let addrMode = PostInc;
[all …]
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| D | HexagonSplitDouble.cpp | 632 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi || in splitMemRef() local
639 unsigned AdrX = PostInc ? (Load ? 2 : 1) in splitMemRef()
644 : (PostInc ? MI->getOperand(3) in splitMemRef()
651 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm(); in splitMemRef()
660 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm(); in splitMemRef()
671 if (PostInc) { in splitMemRef()
|
| D | Hexagon.td | 248 let KeyCol = ["PostInc"];
257 let ValueCols = [["PostInc"]];
|
| D | HexagonRDFOpt.cpp | 221 if (HII.getAddrMode(MI) != HexagonII::PostInc) in rewrite()
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| D | HexagonInstrFormats.td | 20 def PostInc : AddrModeType<6>; // Post increment addressing mode
|
| D | HexagonPseudo.td | 529 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
550 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 34 PostInc = 2, enumerator
415 return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PostInc; in isPostIncrement()
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 34 PostInc = 2, enumerator
415 return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PostInc; in isPostIncrement()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 587 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi || in splitMemRef() local
594 unsigned AdrX = PostInc ? (Load ? 2 : 1) in splitMemRef()
599 : (PostInc ? MI->getOperand(3) in splitMemRef()
606 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm(); in splitMemRef()
615 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm(); in splitMemRef()
626 if (PostInc) { in splitMemRef()
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| D | HexagonRDFOpt.cpp | 207 if (HII.getAddrMode(MI) != HexagonII::PostInc) in rewrite()
|
| D | HexagonInstrInfoV60.td | 337 let addrMode = PostInc, hasNewValue = 1 in
402 let addrMode = PostInc, isPredicable = 1 in
444 let addrMode = PostInc, isNVStore = 1 in
479 let isPredicated = 1, addrMode = PostInc in
542 let addrMode = PostInc in
583 isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 632 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi || in splitMemRef() local
639 unsigned AdrX = PostInc ? (Load ? 2 : 1) in splitMemRef()
644 : (PostInc ? MI->getOperand(3) in splitMemRef()
651 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm(); in splitMemRef()
660 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm(); in splitMemRef()
671 if (PostInc) { in splitMemRef()
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| D | HexagonDepInstrInfo.td | 8876 let addrMode = PostInc;
8888 let addrMode = PostInc;
8901 let addrMode = PostInc;
8914 let addrMode = PostInc;
8926 let addrMode = PostInc;
8964 let addrMode = PostInc;
8976 let addrMode = PostInc;
8989 let addrMode = PostInc;
9002 let addrMode = PostInc;
9014 let addrMode = PostInc;
[all …]
|
| D | Hexagon.td | 277 let KeyCol = ["PostInc"];
286 let ValueCols = [["PostInc"]];
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| D | HexagonRDFOpt.cpp | 221 if (HII.getAddrMode(MI) != HexagonII::PostInc) in rewrite()
|
| D | HexagonPseudo.td | 529 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
552 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
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| D | HexagonInstrFormats.td | 20 def PostInc : AddrModeType<6>; // Post increment addressing mode
|
| /external/llvm-project/clang/include/clang/AST/ |
| D | StmtVisitor.h | 160 UNARYOP_FALLBACK(PostInc) UNARYOP_FALLBACK(PostDec)
|
| /external/clang/include/clang/AST/ |
| D | StmtVisitor.h | 155 UNARYOP_FALLBACK(PostInc) UNARYOP_FALLBACK(PostDec)
|