1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "common/v3d_limits.h"
38 #include "compiler/nir/nir.h"
39 #include "util/list.h"
40 #include "util/u_math.h"
41
42 #include "qpu/qpu_instr.h"
43 #include "pipe/p_state.h"
44
45 struct nir_builder;
46
47 struct v3d_fs_inputs {
48 /**
49 * Array of the meanings of the VPM inputs this shader needs.
50 *
51 * It doesn't include those that aren't part of the VPM, like
52 * point/line coordinates.
53 */
54 struct v3d_varying_slot *input_slots;
55 uint32_t num_inputs;
56 };
57
58 enum qfile {
59 /** An unused source or destination register. */
60 QFILE_NULL,
61
62 /** A physical register, such as the W coordinate payload. */
63 QFILE_REG,
64 /** One of the regsiters for fixed function interactions. */
65 QFILE_MAGIC,
66
67 /**
68 * A virtual register, that will be allocated to actual accumulator
69 * or physical registers later.
70 */
71 QFILE_TEMP,
72
73 /**
74 * VPM reads use this with an index value to say what part of the VPM
75 * is being read.
76 */
77 QFILE_VPM,
78
79 /**
80 * Stores an immediate value in the index field that will be used
81 * directly by qpu_load_imm().
82 */
83 QFILE_LOAD_IMM,
84
85 /**
86 * Stores an immediate value in the index field that can be turned
87 * into a small immediate field by qpu_encode_small_immediate().
88 */
89 QFILE_SMALL_IMM,
90 };
91
92 /**
93 * A reference to a QPU register or a virtual temp register.
94 */
95 struct qreg {
96 enum qfile file;
97 uint32_t index;
98 };
99
vir_reg(enum qfile file,uint32_t index)100 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
101 {
102 return (struct qreg){file, index};
103 }
104
vir_magic_reg(uint32_t index)105 static inline struct qreg vir_magic_reg(uint32_t index)
106 {
107 return (struct qreg){QFILE_MAGIC, index};
108 }
109
vir_nop_reg(void)110 static inline struct qreg vir_nop_reg(void)
111 {
112 return (struct qreg){QFILE_NULL, 0};
113 }
114
115 /**
116 * A reference to an actual register at the QPU level, for register
117 * allocation.
118 */
119 struct qpu_reg {
120 bool magic;
121 bool smimm;
122 int index;
123 };
124
125 struct qinst {
126 /** Entry in qblock->instructions */
127 struct list_head link;
128
129 /**
130 * The instruction being wrapped. Its condition codes, pack flags,
131 * signals, etc. will all be used, with just the register references
132 * being replaced by the contents of qinst->dst and qinst->src[].
133 */
134 struct v3d_qpu_instr qpu;
135
136 /* Pre-register-allocation references to src/dst registers */
137 struct qreg dst;
138 struct qreg src[3];
139 bool is_last_thrsw;
140
141 /* If the instruction reads a uniform (other than through src[i].file
142 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
143 * otherwise.
144 */
145 int uniform;
146 };
147
148 enum quniform_contents {
149 /**
150 * Indicates that a constant 32-bit value is copied from the program's
151 * uniform contents.
152 */
153 QUNIFORM_CONSTANT,
154 /**
155 * Indicates that the program's uniform contents are used as an index
156 * into the GL uniform storage.
157 */
158 QUNIFORM_UNIFORM,
159
160 /** @{
161 * Scaling factors from clip coordinates to relative to the viewport
162 * center.
163 *
164 * This is used by the coordinate and vertex shaders to produce the
165 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
166 * point offsets from the viewport ccenter.
167 */
168 QUNIFORM_VIEWPORT_X_SCALE,
169 QUNIFORM_VIEWPORT_Y_SCALE,
170 /** @} */
171
172 QUNIFORM_VIEWPORT_Z_OFFSET,
173 QUNIFORM_VIEWPORT_Z_SCALE,
174
175 QUNIFORM_USER_CLIP_PLANE,
176
177 /**
178 * A reference to a V3D 3.x texture config parameter 0 uniform.
179 *
180 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
181 * defines texture type, miplevels, and such. It will be found as a
182 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
183 */
184 QUNIFORM_TEXTURE_CONFIG_P0_0,
185 QUNIFORM_TEXTURE_CONFIG_P0_1,
186 QUNIFORM_TEXTURE_CONFIG_P0_2,
187 QUNIFORM_TEXTURE_CONFIG_P0_3,
188 QUNIFORM_TEXTURE_CONFIG_P0_4,
189 QUNIFORM_TEXTURE_CONFIG_P0_5,
190 QUNIFORM_TEXTURE_CONFIG_P0_6,
191 QUNIFORM_TEXTURE_CONFIG_P0_7,
192 QUNIFORM_TEXTURE_CONFIG_P0_8,
193 QUNIFORM_TEXTURE_CONFIG_P0_9,
194 QUNIFORM_TEXTURE_CONFIG_P0_10,
195 QUNIFORM_TEXTURE_CONFIG_P0_11,
196 QUNIFORM_TEXTURE_CONFIG_P0_12,
197 QUNIFORM_TEXTURE_CONFIG_P0_13,
198 QUNIFORM_TEXTURE_CONFIG_P0_14,
199 QUNIFORM_TEXTURE_CONFIG_P0_15,
200 QUNIFORM_TEXTURE_CONFIG_P0_16,
201 QUNIFORM_TEXTURE_CONFIG_P0_17,
202 QUNIFORM_TEXTURE_CONFIG_P0_18,
203 QUNIFORM_TEXTURE_CONFIG_P0_19,
204 QUNIFORM_TEXTURE_CONFIG_P0_20,
205 QUNIFORM_TEXTURE_CONFIG_P0_21,
206 QUNIFORM_TEXTURE_CONFIG_P0_22,
207 QUNIFORM_TEXTURE_CONFIG_P0_23,
208 QUNIFORM_TEXTURE_CONFIG_P0_24,
209 QUNIFORM_TEXTURE_CONFIG_P0_25,
210 QUNIFORM_TEXTURE_CONFIG_P0_26,
211 QUNIFORM_TEXTURE_CONFIG_P0_27,
212 QUNIFORM_TEXTURE_CONFIG_P0_28,
213 QUNIFORM_TEXTURE_CONFIG_P0_29,
214 QUNIFORM_TEXTURE_CONFIG_P0_30,
215 QUNIFORM_TEXTURE_CONFIG_P0_31,
216 QUNIFORM_TEXTURE_CONFIG_P0_32,
217
218 /**
219 * A reference to a V3D 3.x texture config parameter 1 uniform.
220 *
221 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
222 * has the pointer to the indirect texture state. Our data[] field
223 * will have a packed p1 value, but the address field will be just
224 * which texture unit's texture should be referenced.
225 */
226 QUNIFORM_TEXTURE_CONFIG_P1,
227
228 /* A V3D 4.x texture config parameter. The high 8 bits will be
229 * which texture or sampler is being sampled, and the driver must
230 * replace the address field with the appropriate address.
231 */
232 QUNIFORM_TMU_CONFIG_P0,
233 QUNIFORM_TMU_CONFIG_P1,
234
235 QUNIFORM_IMAGE_TMU_CONFIG_P0,
236
237 QUNIFORM_TEXTURE_FIRST_LEVEL,
238
239 QUNIFORM_TEXTURE_WIDTH,
240 QUNIFORM_TEXTURE_HEIGHT,
241 QUNIFORM_TEXTURE_DEPTH,
242 QUNIFORM_TEXTURE_ARRAY_SIZE,
243 QUNIFORM_TEXTURE_LEVELS,
244 QUNIFORM_TEXTURE_SAMPLES,
245
246 QUNIFORM_UBO_ADDR,
247
248 QUNIFORM_TEXRECT_SCALE_X,
249 QUNIFORM_TEXRECT_SCALE_Y,
250
251 /* Returns the base offset of the SSBO given by the data value. */
252 QUNIFORM_SSBO_OFFSET,
253
254 /* Returns the size of the SSBO or UBO given by the data value. */
255 QUNIFORM_GET_SSBO_SIZE,
256 QUNIFORM_GET_UBO_SIZE,
257
258 /* Sizes (in pixels) of a shader image given by the data value. */
259 QUNIFORM_IMAGE_WIDTH,
260 QUNIFORM_IMAGE_HEIGHT,
261 QUNIFORM_IMAGE_DEPTH,
262 QUNIFORM_IMAGE_ARRAY_SIZE,
263
264 QUNIFORM_ALPHA_REF,
265
266 QUNIFORM_LINE_WIDTH,
267
268 /* The line width sent to hardware. This includes the expanded width
269 * when anti-aliasing is enabled.
270 */
271 QUNIFORM_AA_LINE_WIDTH,
272
273 /* Number of workgroups passed to glDispatchCompute in the dimension
274 * selected by the data value.
275 */
276 QUNIFORM_NUM_WORK_GROUPS,
277
278 /**
279 * Returns the the offset of the scratch buffer for register spilling.
280 */
281 QUNIFORM_SPILL_OFFSET,
282 QUNIFORM_SPILL_SIZE_PER_THREAD,
283
284 /**
285 * Returns the offset of the shared memory for compute shaders.
286 *
287 * This will be accessed using TMU general memory operations, so the
288 * L2T cache will effectively be the shared memory area.
289 */
290 QUNIFORM_SHARED_OFFSET,
291
292 /**
293 * Returns the number of layers in the framebuffer.
294 *
295 * This is used to cap gl_Layer in geometry shaders to avoid
296 * out-of-bounds accesses into the tile state during binning.
297 */
298 QUNIFORM_FB_LAYERS,
299 };
300
v3d_unit_data_create(uint32_t unit,uint32_t value)301 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
302 {
303 assert(value < (1 << 24));
304 return unit << 24 | value;
305 }
306
v3d_unit_data_get_unit(uint32_t data)307 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
308 {
309 return data >> 24;
310 }
311
v3d_unit_data_get_offset(uint32_t data)312 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
313 {
314 return data & 0xffffff;
315 }
316
317 struct v3d_varying_slot {
318 uint8_t slot_and_component;
319 };
320
321 static inline struct v3d_varying_slot
v3d_slot_from_slot_and_component(uint8_t slot,uint8_t component)322 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
323 {
324 assert(slot < 255 / 4);
325 return (struct v3d_varying_slot){ (slot << 2) + component };
326 }
327
v3d_slot_get_slot(struct v3d_varying_slot slot)328 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
329 {
330 return slot.slot_and_component >> 2;
331 }
332
v3d_slot_get_component(struct v3d_varying_slot slot)333 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
334 {
335 return slot.slot_and_component & 3;
336 }
337
338 enum v3d_execution_environment {
339 V3D_ENVIRONMENT_OPENGL = 0,
340 V3D_ENVIRONMENT_VULKAN,
341 };
342
343 struct v3d_key {
344 void *shader_state;
345 struct {
346 uint8_t swizzle[4];
347 uint8_t return_size;
348 uint8_t return_channels;
349 bool clamp_s:1;
350 bool clamp_t:1;
351 bool clamp_r:1;
352 } tex[V3D_MAX_TEXTURE_SAMPLERS];
353 uint8_t num_tex_used;
354 uint8_t ucp_enables;
355 bool is_last_geometry_stage;
356 bool robust_buffer_access;
357
358 enum v3d_execution_environment environment;
359 };
360
361 struct v3d_fs_key {
362 struct v3d_key base;
363 bool is_points;
364 bool is_lines;
365 bool line_smoothing;
366 bool alpha_test;
367 bool point_coord_upper_left;
368 bool light_twoside;
369 bool msaa;
370 bool sample_coverage;
371 bool sample_alpha_to_coverage;
372 bool sample_alpha_to_one;
373 bool clamp_color;
374 bool shade_model_flat;
375 /* Mask of which color render targets are present. */
376 uint8_t cbufs;
377 uint8_t swap_color_rb;
378 /* Mask of which render targets need to be written as 32-bit floats */
379 uint8_t f32_color_rb;
380 /* Masks of which render targets need to be written as ints/uints.
381 * Used by gallium to work around lost information in TGSI.
382 */
383 uint8_t int_color_rb;
384 uint8_t uint_color_rb;
385
386 /* Color format information per render target. Only set when logic
387 * operations are enabled.
388 */
389 struct {
390 enum pipe_format format;
391 const uint8_t *swizzle;
392 } color_fmt[V3D_MAX_DRAW_BUFFERS];
393
394 uint8_t alpha_test_func;
395 uint8_t logicop_func;
396 uint32_t point_sprite_mask;
397
398 struct pipe_rt_blend_state blend;
399 };
400
401 struct v3d_gs_key {
402 struct v3d_key base;
403
404 struct v3d_varying_slot used_outputs[V3D_MAX_FS_INPUTS];
405 uint8_t num_used_outputs;
406
407 bool is_coord;
408 bool per_vertex_point_size;
409 };
410
411 struct v3d_vs_key {
412 struct v3d_key base;
413
414 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
415 uint8_t num_used_outputs;
416
417 /* A bit-mask indicating if we need to swap the R/B channels for
418 * vertex attributes. Since the hardware doesn't provide any
419 * means to swizzle vertex attributes we need to do it in the shader.
420 */
421 uint32_t va_swap_rb_mask;
422
423 bool is_coord;
424 bool per_vertex_point_size;
425 bool clamp_color;
426 };
427
428 /** A basic block of VIR intructions. */
429 struct qblock {
430 struct list_head link;
431
432 struct list_head instructions;
433
434 struct set *predecessors;
435 struct qblock *successors[2];
436
437 int index;
438
439 /* Instruction IPs for the first and last instruction of the block.
440 * Set by qpu_schedule.c.
441 */
442 uint32_t start_qpu_ip;
443 uint32_t end_qpu_ip;
444
445 /* Instruction IP for the branch instruction of the block. Set by
446 * qpu_schedule.c.
447 */
448 uint32_t branch_qpu_ip;
449
450 /** Offset within the uniform stream at the start of the block. */
451 uint32_t start_uniform;
452 /** Offset within the uniform stream of the branch instruction */
453 uint32_t branch_uniform;
454
455 /** @{ used by v3d_vir_live_variables.c */
456 BITSET_WORD *def;
457 BITSET_WORD *defin;
458 BITSET_WORD *defout;
459 BITSET_WORD *use;
460 BITSET_WORD *live_in;
461 BITSET_WORD *live_out;
462 int start_ip, end_ip;
463 /** @} */
464 };
465
466 /** Which util/list.h add mode we should use when inserting an instruction. */
467 enum vir_cursor_mode {
468 vir_cursor_add,
469 vir_cursor_addtail,
470 };
471
472 /**
473 * Tracking structure for where new instructions should be inserted. Create
474 * with one of the vir_after_inst()-style helper functions.
475 *
476 * This does not protect against removal of the block or instruction, so we
477 * have an assert in instruction removal to try to catch it.
478 */
479 struct vir_cursor {
480 enum vir_cursor_mode mode;
481 struct list_head *link;
482 };
483
484 static inline struct vir_cursor
vir_before_inst(struct qinst * inst)485 vir_before_inst(struct qinst *inst)
486 {
487 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
488 }
489
490 static inline struct vir_cursor
vir_after_inst(struct qinst * inst)491 vir_after_inst(struct qinst *inst)
492 {
493 return (struct vir_cursor){ vir_cursor_add, &inst->link };
494 }
495
496 static inline struct vir_cursor
vir_before_block(struct qblock * block)497 vir_before_block(struct qblock *block)
498 {
499 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
500 }
501
502 static inline struct vir_cursor
vir_after_block(struct qblock * block)503 vir_after_block(struct qblock *block)
504 {
505 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
506 }
507
508 enum v3d_compilation_result {
509 V3D_COMPILATION_SUCCEEDED,
510 V3D_COMPILATION_FAILED_REGISTER_ALLOCATION,
511 V3D_COMPILATION_FAILED,
512 };
513
514 /**
515 * Compiler state saved across compiler invocations, for any expensive global
516 * setup.
517 */
518 struct v3d_compiler {
519 const struct v3d_device_info *devinfo;
520 struct ra_regs *regs;
521 unsigned int reg_class_any[3];
522 unsigned int reg_class_r5[3];
523 unsigned int reg_class_phys[3];
524 unsigned int reg_class_phys_or_acc[3];
525 };
526
527 /**
528 * This holds partially interpolated inputs as provided by hardware
529 * (The Vp = A*(x - x0) + B*(y - y0) term), as well as the C coefficient
530 * required to compute the final interpolated value.
531 */
532 struct v3d_interp_input {
533 struct qreg vp;
534 struct qreg C;
535 unsigned mode; /* interpolation mode */
536 };
537
538 struct v3d_compile {
539 const struct v3d_device_info *devinfo;
540 nir_shader *s;
541 nir_function_impl *impl;
542 struct exec_list *cf_node_list;
543 const struct v3d_compiler *compiler;
544
545 void (*debug_output)(const char *msg,
546 void *debug_output_data);
547 void *debug_output_data;
548
549 /**
550 * Mapping from nir_register * or nir_ssa_def * to array of struct
551 * qreg for the values.
552 */
553 struct hash_table *def_ht;
554
555 /* For each temp, the instruction generating its value. */
556 struct qinst **defs;
557 uint32_t defs_array_size;
558
559 /**
560 * Inputs to the shader, arranged by TGSI declaration order.
561 *
562 * Not all fragment shader QFILE_VARY reads are present in this array.
563 */
564 struct qreg *inputs;
565 /**
566 * Partially interpolated inputs to the shader.
567 */
568 struct v3d_interp_input *interp;
569 struct qreg *outputs;
570 bool msaa_per_sample_output;
571 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
572 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
573 uint32_t inputs_array_size;
574 uint32_t outputs_array_size;
575 uint32_t uniforms_array_size;
576
577 /* Booleans for whether the corresponding QFILE_VARY[i] is
578 * flat-shaded. This includes gl_FragColor flat-shading, which is
579 * customized based on the shademodel_flat shader key.
580 */
581 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
582
583 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
584
585 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
586
587 bool uses_center_w;
588 bool writes_z;
589 bool uses_implicit_point_line_varyings;
590
591 /* If the fragment shader does anything that requires to force
592 * per-sample MSAA, such as reading gl_SampleID.
593 */
594 bool force_per_sample_msaa;
595
596 /* Whether we are using the fallback scheduler. This will be set after
597 * register allocation has failed once.
598 */
599 bool fallback_scheduler;
600
601 /* State for whether we're executing on each channel currently. 0 if
602 * yes, otherwise a block number + 1 that the channel jumped to.
603 */
604 struct qreg execute;
605 bool in_control_flow;
606
607 struct qreg line_x, point_x, point_y;
608
609 /**
610 * Instance ID, which comes in before the vertex attribute payload if
611 * the shader record requests it.
612 */
613 struct qreg iid;
614
615 /**
616 * Base Instance ID, which comes in before the vertex attribute payload
617 * (after Instance ID) if the shader record requests it.
618 */
619 struct qreg biid;
620
621 /**
622 * Vertex ID, which comes in before the vertex attribute payload
623 * (after Base Instance) if the shader record requests it.
624 */
625 struct qreg vid;
626
627 /* Fragment shader payload regs. */
628 struct qreg payload_w, payload_w_centroid, payload_z;
629
630 struct qreg cs_payload[2];
631 struct qreg cs_shared_offset;
632 int local_invocation_index_bits;
633
634 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
635 uint32_t vpm_output_size;
636
637 /* Size in bytes of registers that have been spilled. This is how much
638 * space needs to be available in the spill BO per thread per QPU.
639 */
640 uint32_t spill_size;
641 /* Shader-db stats */
642 uint32_t spills, fills, loops;
643 /**
644 * Register spilling's per-thread base address, shared between each
645 * spill/fill's addressing calculations.
646 */
647 struct qreg spill_base;
648 /* Bit vector of which temps may be spilled */
649 BITSET_WORD *spillable;
650
651 /**
652 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
653 *
654 * This includes those that aren't part of the VPM varyings, like
655 * point/line coordinates.
656 */
657 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
658
659 /**
660 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
661 * of the output is. Used to emit from the VS in the order that the
662 * FS needs.
663 */
664 struct v3d_varying_slot *output_slots;
665
666 struct pipe_shader_state *shader_state;
667 struct v3d_key *key;
668 struct v3d_fs_key *fs_key;
669 struct v3d_gs_key *gs_key;
670 struct v3d_vs_key *vs_key;
671
672 /* Live ranges of temps. */
673 int *temp_start, *temp_end;
674 bool live_intervals_valid;
675
676 uint32_t *uniform_data;
677 enum quniform_contents *uniform_contents;
678 uint32_t uniform_array_size;
679 uint32_t num_uniforms;
680 uint32_t output_position_index;
681 nir_variable *output_color_var[4];
682 uint32_t output_sample_mask_index;
683
684 struct qreg undef;
685 uint32_t num_temps;
686
687 struct vir_cursor cursor;
688 struct list_head blocks;
689 int next_block_index;
690 struct qblock *cur_block;
691 struct qblock *loop_cont_block;
692 struct qblock *loop_break_block;
693
694 uint64_t *qpu_insts;
695 uint32_t qpu_inst_count;
696 uint32_t qpu_inst_size;
697 uint32_t qpu_inst_stalled_count;
698
699 /* For the FS, the number of varying inputs not counting the
700 * point/line varyings payload
701 */
702 uint32_t num_inputs;
703
704 uint32_t program_id;
705 uint32_t variant_id;
706
707 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
708 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
709 * limiting ourselves to the part of the physical reg space.
710 *
711 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
712 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
713 * physical reg space in half.
714 */
715 uint8_t threads;
716 struct qinst *last_thrsw;
717 bool last_thrsw_at_top_level;
718
719 bool emitted_tlb_load;
720 bool lock_scoreboard_on_first_thrsw;
721
722 /* Total number of spilled registers in the program */
723 uint32_t spill_count;
724
725 enum v3d_compilation_result compilation_result;
726
727 bool tmu_dirty_rcl;
728 };
729
730 struct v3d_uniform_list {
731 enum quniform_contents *contents;
732 uint32_t *data;
733 uint32_t count;
734 };
735
736 struct v3d_prog_data {
737 struct v3d_uniform_list uniforms;
738
739 uint32_t spill_size;
740
741 uint8_t threads;
742
743 /* For threads > 1, whether the program should be dispatched in the
744 * after-final-THRSW state.
745 */
746 bool single_seg;
747
748 bool tmu_dirty_rcl;
749 };
750
751 struct v3d_vs_prog_data {
752 struct v3d_prog_data base;
753
754 bool uses_iid, uses_biid, uses_vid;
755
756 /* Number of components read from each vertex attribute. */
757 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
758
759 /* Total number of components read, for the shader state record. */
760 uint32_t vpm_input_size;
761
762 /* Total number of components written, for the shader state record. */
763 uint32_t vpm_output_size;
764
765 /* Set if there should be separate VPM segments for input and output.
766 * If unset, vpm_input_size will be 0.
767 */
768 bool separate_segments;
769
770 /* Value to be programmed in VCM_CACHE_SIZE. */
771 uint8_t vcm_cache_size;
772 };
773
774 struct v3d_gs_prog_data {
775 struct v3d_prog_data base;
776
777 /* Whether the program reads gl_PrimitiveIDIn */
778 bool uses_pid;
779
780 /* Number of components read from each input varying. */
781 uint8_t input_sizes[V3D_MAX_GS_INPUTS / 4];
782
783 /* Number of inputs */
784 uint8_t num_inputs;
785 struct v3d_varying_slot input_slots[V3D_MAX_GS_INPUTS];
786
787 /* Total number of components written, for the shader state record. */
788 uint32_t vpm_output_size;
789
790 /* Maximum SIMD dispatch width to not exceed VPM output size limits
791 * in the geometry shader. Notice that the final dispatch width has to
792 * be decided at draw time and could be lower based on the VPM pressure
793 * added by other shader stages.
794 */
795 uint8_t simd_width;
796
797 /* Output primitive type */
798 uint8_t out_prim_type;
799
800 /* Number of GS invocations */
801 uint8_t num_invocations;
802 };
803
804 struct v3d_fs_prog_data {
805 struct v3d_prog_data base;
806
807 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
808
809 /* Array of flat shade flags.
810 *
811 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
812 * packet layout.
813 */
814 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
815
816 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
817
818 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
819
820 uint8_t num_inputs;
821 bool writes_z;
822 bool disable_ez;
823 bool uses_center_w;
824 bool uses_implicit_point_line_varyings;
825 bool lock_scoreboard_on_first_thrsw;
826 bool force_per_sample_msaa;
827 };
828
829 struct v3d_compute_prog_data {
830 struct v3d_prog_data base;
831 /* Size in bytes of the workgroup's shared space. */
832 uint32_t shared_size;
833 };
834
835 static inline bool
vir_has_uniform(struct qinst * inst)836 vir_has_uniform(struct qinst *inst)
837 {
838 return inst->uniform != ~0;
839 }
840
841 extern const nir_shader_compiler_options v3d_nir_options;
842
843 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
844 void v3d_compiler_free(const struct v3d_compiler *compiler);
845 void v3d_optimize_nir(struct nir_shader *s);
846
847 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
848 struct v3d_key *key,
849 struct v3d_prog_data **prog_data,
850 nir_shader *s,
851 void (*debug_output)(const char *msg,
852 void *debug_output_data),
853 void *debug_output_data,
854 int program_id, int variant_id,
855 uint32_t *final_assembly_size);
856
857 uint32_t v3d_prog_data_size(gl_shader_stage stage);
858 void v3d_nir_to_vir(struct v3d_compile *c);
859
860 void vir_compile_destroy(struct v3d_compile *c);
861 const char *vir_get_stage_name(struct v3d_compile *c);
862 struct qblock *vir_new_block(struct v3d_compile *c);
863 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
864 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
865 struct qblock *vir_entry_block(struct v3d_compile *c);
866 struct qblock *vir_exit_block(struct v3d_compile *c);
867 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
868 struct qreg src0, struct qreg src1);
869 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
870 struct qreg src0, struct qreg src1);
871 struct qinst *vir_branch_inst(struct v3d_compile *c,
872 enum v3d_qpu_branch_cond cond);
873 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
874 uint32_t vir_get_uniform_index(struct v3d_compile *c,
875 enum quniform_contents contents,
876 uint32_t data);
877 struct qreg vir_uniform(struct v3d_compile *c,
878 enum quniform_contents contents,
879 uint32_t data);
880 void vir_schedule_instructions(struct v3d_compile *c);
881 void v3d_setup_spill_base(struct v3d_compile *c);
882 struct v3d_qpu_instr v3d_qpu_nop(void);
883
884 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
885 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
886 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
887 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
888 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
889 void vir_set_unpack(struct qinst *inst, int src,
890 enum v3d_qpu_input_unpack unpack);
891 void vir_set_pack(struct qinst *inst, enum v3d_qpu_output_pack pack);
892
893 struct qreg vir_get_temp(struct v3d_compile *c);
894 void vir_emit_last_thrsw(struct v3d_compile *c);
895 void vir_calculate_live_intervals(struct v3d_compile *c);
896 int vir_get_nsrc(struct qinst *inst);
897 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
898 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
899 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
900 bool vir_is_raw_mov(struct qinst *inst);
901 bool vir_is_tex(struct qinst *inst);
902 bool vir_is_add(struct qinst *inst);
903 bool vir_is_mul(struct qinst *inst);
904 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
905 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
906 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
907 uint8_t vir_channels_written(struct qinst *inst);
908 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
909 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
910 struct qreg result);
911 void vir_emit_thrsw(struct v3d_compile *c);
912
913 void vir_dump(struct v3d_compile *c);
914 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
915 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
916
917 void vir_validate(struct v3d_compile *c);
918
919 void vir_optimize(struct v3d_compile *c);
920 bool vir_opt_algebraic(struct v3d_compile *c);
921 bool vir_opt_constant_folding(struct v3d_compile *c);
922 bool vir_opt_copy_propagate(struct v3d_compile *c);
923 bool vir_opt_dead_code(struct v3d_compile *c);
924 bool vir_opt_peephole_sf(struct v3d_compile *c);
925 bool vir_opt_redundant_flags(struct v3d_compile *c);
926 bool vir_opt_small_immediates(struct v3d_compile *c);
927 bool vir_opt_vpm(struct v3d_compile *c);
928 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
929 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
930 void v3d_nir_lower_line_smooth(nir_shader *shader);
931 void v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
932 void v3d_nir_lower_robust_buffer_access(nir_shader *shader, struct v3d_compile *c);
933 void v3d_nir_lower_scratch(nir_shader *s);
934 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
935 void v3d_nir_lower_image_load_store(nir_shader *s);
936 void vir_lower_uniforms(struct v3d_compile *c);
937
938 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
939 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
940 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
941 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
942 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
943 nir_intrinsic_instr *instr);
944
945 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
946 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
947 void qpu_validate(struct v3d_compile *c);
948 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
949 bool vir_init_reg_sets(struct v3d_compiler *compiler);
950
951 int v3d_shaderdb_dump(struct v3d_compile *c, char **shaderdb_str);
952
953 bool v3d_gl_format_is_return_32(GLenum format);
954
955 uint32_t
956 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
957
958 static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)959 quniform_contents_is_texture_p0(enum quniform_contents contents)
960 {
961 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
962 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
963 V3D_MAX_TEXTURE_SAMPLERS));
964 }
965
966 static inline bool
vir_in_nonuniform_control_flow(struct v3d_compile * c)967 vir_in_nonuniform_control_flow(struct v3d_compile *c)
968 {
969 return c->execute.file != QFILE_NULL;
970 }
971
972 static inline struct qreg
vir_uniform_ui(struct v3d_compile * c,uint32_t ui)973 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
974 {
975 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
976 }
977
978 static inline struct qreg
vir_uniform_f(struct v3d_compile * c,float f)979 vir_uniform_f(struct v3d_compile *c, float f)
980 {
981 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
982 }
983
984 #define VIR_ALU0(name, vir_inst, op) \
985 static inline struct qreg \
986 vir_##name(struct v3d_compile *c) \
987 { \
988 return vir_emit_def(c, vir_inst(op, c->undef, \
989 c->undef, c->undef)); \
990 } \
991 static inline struct qinst * \
992 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
993 { \
994 return vir_emit_nondef(c, vir_inst(op, dest, \
995 c->undef, c->undef)); \
996 }
997
998 #define VIR_ALU1(name, vir_inst, op) \
999 static inline struct qreg \
1000 vir_##name(struct v3d_compile *c, struct qreg a) \
1001 { \
1002 return vir_emit_def(c, vir_inst(op, c->undef, \
1003 a, c->undef)); \
1004 } \
1005 static inline struct qinst * \
1006 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1007 struct qreg a) \
1008 { \
1009 return vir_emit_nondef(c, vir_inst(op, dest, a, \
1010 c->undef)); \
1011 }
1012
1013 #define VIR_ALU2(name, vir_inst, op) \
1014 static inline struct qreg \
1015 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1016 { \
1017 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
1018 } \
1019 static inline struct qinst * \
1020 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1021 struct qreg a, struct qreg b) \
1022 { \
1023 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
1024 }
1025
1026 #define VIR_NODST_0(name, vir_inst, op) \
1027 static inline struct qinst * \
1028 vir_##name(struct v3d_compile *c) \
1029 { \
1030 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1031 c->undef, c->undef)); \
1032 }
1033
1034 #define VIR_NODST_1(name, vir_inst, op) \
1035 static inline struct qinst * \
1036 vir_##name(struct v3d_compile *c, struct qreg a) \
1037 { \
1038 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1039 a, c->undef)); \
1040 }
1041
1042 #define VIR_NODST_2(name, vir_inst, op) \
1043 static inline struct qinst * \
1044 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1045 { \
1046 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1047 a, b)); \
1048 }
1049
1050 #define VIR_SFU(name) \
1051 static inline struct qreg \
1052 vir_##name(struct v3d_compile *c, struct qreg a) \
1053 { \
1054 if (c->devinfo->ver >= 41) { \
1055 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1056 c->undef, \
1057 a, c->undef)); \
1058 } else { \
1059 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
1060 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
1061 } \
1062 } \
1063 static inline struct qinst * \
1064 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1065 struct qreg a) \
1066 { \
1067 if (c->devinfo->ver >= 41) { \
1068 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1069 dest, \
1070 a, c->undef)); \
1071 } else { \
1072 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
1073 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
1074 } \
1075 }
1076
1077 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1078 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1079 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1080 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1081 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1082 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1083 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1084 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1085 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1086 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1087 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1088
1089 VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)1090 VIR_A_ALU2(VFPACK)
1091 VIR_A_ALU2(FSUB)
1092 VIR_A_ALU2(FMIN)
1093 VIR_A_ALU2(FMAX)
1094
1095 VIR_A_ALU2(ADD)
1096 VIR_A_ALU2(SUB)
1097 VIR_A_ALU2(SHL)
1098 VIR_A_ALU2(SHR)
1099 VIR_A_ALU2(ASR)
1100 VIR_A_ALU2(ROR)
1101 VIR_A_ALU2(MIN)
1102 VIR_A_ALU2(MAX)
1103 VIR_A_ALU2(UMIN)
1104 VIR_A_ALU2(UMAX)
1105 VIR_A_ALU2(AND)
1106 VIR_A_ALU2(OR)
1107 VIR_A_ALU2(XOR)
1108 VIR_A_ALU2(VADD)
1109 VIR_A_ALU2(VSUB)
1110 VIR_A_NODST_2(STVPMV)
1111 VIR_A_NODST_2(STVPMD)
1112 VIR_A_ALU1(NOT)
1113 VIR_A_ALU1(NEG)
1114 VIR_A_ALU1(FLAPUSH)
1115 VIR_A_ALU1(FLBPUSH)
1116 VIR_A_ALU1(FLPOP)
1117 VIR_A_ALU1(SETMSF)
1118 VIR_A_ALU1(SETREVF)
1119 VIR_A_ALU0(TIDX)
1120 VIR_A_ALU0(EIDX)
1121 VIR_A_ALU1(LDVPMV_IN)
1122 VIR_A_ALU1(LDVPMV_OUT)
1123 VIR_A_ALU1(LDVPMD_IN)
1124 VIR_A_ALU1(LDVPMD_OUT)
1125 VIR_A_ALU2(LDVPMG_IN)
1126 VIR_A_ALU2(LDVPMG_OUT)
1127 VIR_A_ALU0(TMUWT)
1128
1129 VIR_A_ALU0(IID)
1130 VIR_A_ALU0(FXCD)
1131 VIR_A_ALU0(XCD)
1132 VIR_A_ALU0(FYCD)
1133 VIR_A_ALU0(YCD)
1134 VIR_A_ALU0(MSF)
1135 VIR_A_ALU0(REVF)
1136 VIR_A_ALU0(BARRIERID)
1137 VIR_A_ALU0(SAMPID)
1138 VIR_A_NODST_1(VPMSETUP)
1139 VIR_A_NODST_0(VPMWT)
1140 VIR_A_ALU2(FCMP)
1141 VIR_A_ALU2(VFMAX)
1142
1143 VIR_A_ALU1(FROUND)
1144 VIR_A_ALU1(FTOIN)
1145 VIR_A_ALU1(FTRUNC)
1146 VIR_A_ALU1(FTOIZ)
1147 VIR_A_ALU1(FFLOOR)
1148 VIR_A_ALU1(FTOUZ)
1149 VIR_A_ALU1(FCEIL)
1150 VIR_A_ALU1(FTOC)
1151
1152 VIR_A_ALU1(FDX)
1153 VIR_A_ALU1(FDY)
1154
1155 VIR_A_ALU1(ITOF)
1156 VIR_A_ALU1(CLZ)
1157 VIR_A_ALU1(UTOF)
1158
1159 VIR_M_ALU2(UMUL24)
1160 VIR_M_ALU2(FMUL)
1161 VIR_M_ALU2(SMUL24)
1162 VIR_M_NODST_2(MULTOP)
1163
1164 VIR_M_ALU1(MOV)
1165 VIR_M_ALU1(FMOV)
1166
1167 VIR_SFU(RECIP)
1168 VIR_SFU(RSQRT)
1169 VIR_SFU(EXP)
1170 VIR_SFU(LOG)
1171 VIR_SFU(SIN)
1172 VIR_SFU(RSQRT2)
1173
1174 static inline struct qinst *
1175 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1176 struct qreg dest, struct qreg src)
1177 {
1178 struct qinst *mov = vir_MOV_dest(c, dest, src);
1179 vir_set_cond(mov, cond);
1180 return mov;
1181 }
1182
1183 static inline struct qreg
vir_SEL(struct v3d_compile * c,enum v3d_qpu_cond cond,struct qreg src0,struct qreg src1)1184 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1185 struct qreg src0, struct qreg src1)
1186 {
1187 struct qreg t = vir_get_temp(c);
1188 vir_MOV_dest(c, t, src1);
1189 vir_MOV_cond(c, cond, t, src0);
1190 return t;
1191 }
1192
1193 static inline struct qinst *
vir_NOP(struct v3d_compile * c)1194 vir_NOP(struct v3d_compile *c)
1195 {
1196 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1197 c->undef, c->undef, c->undef));
1198 }
1199
1200 static inline struct qreg
vir_LDTMU(struct v3d_compile * c)1201 vir_LDTMU(struct v3d_compile *c)
1202 {
1203 if (c->devinfo->ver >= 41) {
1204 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1205 c->undef, c->undef);
1206 ldtmu->qpu.sig.ldtmu = true;
1207
1208 return vir_emit_def(c, ldtmu);
1209 } else {
1210 vir_NOP(c)->qpu.sig.ldtmu = true;
1211 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1212 }
1213 }
1214
1215 static inline struct qreg
vir_UMUL(struct v3d_compile * c,struct qreg src0,struct qreg src1)1216 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1217 {
1218 vir_MULTOP(c, src0, src1);
1219 return vir_UMUL24(c, src0, src1);
1220 }
1221
1222 static inline struct qreg
vir_TLBU_COLOR_READ(struct v3d_compile * c,uint32_t config)1223 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1224 {
1225 assert(c->devinfo->ver >= 41); /* XXX */
1226 assert((config & 0xffffff00) == 0xffffff00);
1227
1228 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1229 c->undef, c->undef);
1230 ldtlb->qpu.sig.ldtlbu = true;
1231 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1232 return vir_emit_def(c, ldtlb);
1233 }
1234
1235 static inline struct qreg
vir_TLB_COLOR_READ(struct v3d_compile * c)1236 vir_TLB_COLOR_READ(struct v3d_compile *c)
1237 {
1238 assert(c->devinfo->ver >= 41); /* XXX */
1239
1240 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1241 c->undef, c->undef);
1242 ldtlb->qpu.sig.ldtlb = true;
1243 return vir_emit_def(c, ldtlb);
1244 }
1245
1246 /*
1247 static inline struct qreg
1248 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1249 {
1250 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1251 vir_reg(QFILE_LOAD_IMM, val), c->undef));
1252 }
1253
1254 static inline struct qreg
1255 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1256 {
1257 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1258 vir_reg(QFILE_LOAD_IMM, val),
1259 c->undef));
1260 }
1261 static inline struct qreg
1262 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1263 {
1264 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1265 vir_reg(QFILE_LOAD_IMM, val),
1266 c->undef));
1267 }
1268 */
1269
1270 static inline struct qinst *
vir_BRANCH(struct v3d_compile * c,enum v3d_qpu_branch_cond cond)1271 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1272 {
1273 /* The actual uniform_data value will be set at scheduling time */
1274 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1275 }
1276
1277 #define vir_for_each_block(block, c) \
1278 list_for_each_entry(struct qblock, block, &c->blocks, link)
1279
1280 #define vir_for_each_block_rev(block, c) \
1281 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1282
1283 /* Loop over the non-NULL members of the successors array. */
1284 #define vir_for_each_successor(succ, block) \
1285 for (struct qblock *succ = block->successors[0]; \
1286 succ != NULL; \
1287 succ = (succ == block->successors[1] ? NULL : \
1288 block->successors[1]))
1289
1290 #define vir_for_each_inst(inst, block) \
1291 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1292
1293 #define vir_for_each_inst_rev(inst, block) \
1294 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1295
1296 #define vir_for_each_inst_safe(inst, block) \
1297 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1298
1299 #define vir_for_each_inst_inorder(inst, c) \
1300 vir_for_each_block(_block, c) \
1301 vir_for_each_inst(inst, _block)
1302
1303 #define vir_for_each_inst_inorder_safe(inst, c) \
1304 vir_for_each_block(_block, c) \
1305 vir_for_each_inst_safe(inst, _block)
1306
1307 #endif /* V3D_COMPILER_H */
1308